Processor Configuration Registers
2.18.14 PMEN_REG—Protected Memory Enable Register
This register enables the DMA-protected memory regions setup through the PLMBASE,
PLMLIMT, PHMBASE, PHMLIMIT registers. This register is always treated as RO for
implementations not supporting protected memory regions (PLMR and PHMR fields
reported as Clear in the Capability register).
Protected memory regions may be used by software to securely initialize remapping
structures in memory. To avoid impact to legacy BIOS usage of memory, software is
recommended to not overlap protected memory regions with any reserved memory
regions of the platform reported through the Reserved Memory Region Reporting
(RMRR) structures.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/GFXVTBAR
64–67h
00000000h
RW, RO-V
32 bits
00000000h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
Enable Protected Memory (EPM)
This field controls DMA accesses to the protected low-memory
and protected high-memory regions.
0 = Protected memory regions are disabled.
1 = Protected memory regions are enabled. DMA requests
accessing protected memory regions are handled as follows:
— When DMA remapping is not enabled, all DMA requests
accessing protected memory regions are blocked.
— When DMA remapping is enabled:
• DMA requests processed as pass-through
(Translation Type value of 10b in Context-Entry) and
accessing the protected memory regions are blocked.
• DMA requests with translated address (AT=10b) and
accessing the protected memory regions are blocked.
• DMA requests that are subject to address remapping,
and accessing the protected memory regions may or
may not be blocked by hardware. For such requests,
software must not depend on hardware protection of
the protected memory regions, and instead program
the DMA-remapping page-tables to not allow DMA to
protected memory regions.
31
RW
0h
Uncore
Remapping hardware access to the remapping structures are not
subject to protected memory region checks.
DMA requests blocked due to protected memory region violation
are not recorded or reported as remapping faults.
Hardware reports the status of the protected memory
enable/disable operation through the PRS field in this register.
Hardware implementations supporting DMA draining must drain
any in-flight translated DMA requests queued within the Root-
Complex before indicating the protected memory region as
enabled through the PRS field.
30:1
0
RO
0h
0h
Reserved (RSVD)
Protected Region Status (PRS)
This field indicates the status of protected memory regions:
0 = Protected memory region(s) disabled.
1 = Protected memory region(s) enabled.
RO-V
Uncore
280
Datasheet, Volume 2
INTEL [ INTEL ]
