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326769-002 参数 Datasheet PDF下载

326769-002图片预览
型号: 326769-002
PDF下载: 下载PDF文件 查看货源
内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
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Processor Configuration Registers  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/0/0/GFXVTBAR  
18–1Bh  
00000000h  
RO, WO  
32 bits  
Size:  
BIOS Optimal Default  
000000h  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
Write Buffer Flush (WBF)  
This bit is valid only for implementations requiring write buffer  
flushing.  
Software sets this field to request that hardware flush the Root-  
Complex internal write buffers. This is done to ensure any  
updates to the memory-resident remapping structures are not  
held in any internal write posting buffers.  
27  
RO  
0b  
Uncore  
Hardware reports the status of the write buffer flushing operation  
through the WBFS field in the Global Status register.  
Clearing this bit has no effect. The value returned on a read of  
this field is undefined.  
Queued Invalidation Enable (QIE)  
This field is valid only for implementations supporting queued  
invalidations.  
Software writes to this field to enable or disable queued  
invalidations.  
0 = Disable queued invalidations.  
26  
WO  
0b  
Uncore  
1 = Enable use of queued invalidations.  
Hardware reports the status of queued invalidation enable  
operation through QIES field in the Global Status register.  
The value returned on a read of this field is undefined.  
Interrupt Remapping Enable (IRE)  
This field is valid only for implementations supporting interrupt  
remapping.  
0 = Disable interrupt-remapping hardware  
1 = Enable interrupt-remapping hardware  
Hardware reports the status of the interrupt remapping enable  
operation through the IRES field in the Global Status register.  
There may be active interrupt requests in the platform when  
software updates this field. Hardware must enable or disable  
interrupt-remapping logic only at deterministic transaction  
boundaries, so that any in-flight interrupts are either subject to  
remapping or not at all.  
25  
WO  
0b  
Uncore  
Hardware implementations must drain any in-flight interrupts  
requests queued in the Root-Complex before completing the  
interrupt-remapping enable command and reflecting the status of  
the command through the IRES field in the Global Status register.  
The value returned on a read of this field is undefined.  
Datasheet, Volume 2  
269