Signal Description
2.25
Pin Straps
2.25.1
Functional Straps
The following signals are used for static configuration. They are sampled at the rising
edge of PWROK to select configurations (except as noted), and then revert later to their
normal usage. To invoke the associated mode, the signal should be driven at least four
PCI clocks prior to the time it is sampled.
The ICH10 has implemented Soft Straps. Soft Straps are used to configure specific
functions within the ICH and (G)MCH very early in the boot process before BIOS or SW
intervention. When Descriptor Mode is enabled, the ICH will read Soft Strap data out of
the SPI device prior to the de-assertion of reset to both the Intel Management Engine
and the Host system. Refer to Section 5.23.2 for information on Descriptor Mode and
Section for more information on Soft Straps and their settings.
Table 2-25. Functional Strap Definitions (Sheet 1 of 4)
When
Signal
Usage
Comment
Sampled
XOR Chain
Entrance
Rising Edge of
PWROK
Allows entrance to XOR Chain testing when
TP3 pulled low at rising edge of PWROK.
HDA_SDOUT
PCI Express*
Port Config 1
bit 1 (Port 1-4)
(Consumer
Only)
When TP3 not pulled low at rising edge of
Rising Edge of PWROK, sets bit 1 of RPC.PC (Chipset
HDA_SDOUT
PWROK
Config Registers:Offset 224h).This signal
has a weak internal pull-down.
This signal has a weak internal pull-down.
PCI Express
Port Config 1
bit 0 (Port 1-4)
HDA_SYNC
(Consumer Only)
Rising Edge of
PWROK
Sets bit 0 of RPC.PC (Chipset Config
Registers:Offset 224h)
This signal has a weak internal pull-up.
PCI Express
Port Config 2
bit 2 (Port 5-6)
GNT2# / GPIO53
(Consumer Only)
Rising Edge of
PWROK
Sets bit 2 of RPC.PC2 (Chipset Config
Registers:Offset 0224h) when sampled low.
Rising Edge of This signal has a weak internal pull-down.
GPIO20
Reserved
PWROK
NOTE: This signal should not be pulled high
Tying this strap low configures DMI for ESI-
compatible operation. This signal has a
Rising edge of weak internal pull-up.
ESI Strap
(Server/
Workstation
Only)
GNT1#/GPIO51
PWROK
NOTE: ESI compatible mode is for server
platforms only. This signal should
not be pulled low for desktop.
The signal has a weak internal pull-up. If
the signal is sampled low, this indicates
that the system is strapped to the “top-
block swap” mode (Intel ICH10 inverts A16
for all cycles targeting BIOS space). The
status of this strap is readable via the Top
Swap bit (Chipset Config Registers:Offset
3414h:bit 0). Note that software will not be
able to clear the Top-Swap bit until the
system is rebooted without GNT3# being
pulled down.
Top-Block
Swap Override
Rising Edge of
PWROK
GNT3# / GPIO55
Datasheet
75
INTEL [ INTEL ]
