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319973-003 参数 Datasheet PDF下载

319973-003图片预览
型号: 319973-003
PDF下载: 下载PDF文件 查看货源
内容描述: 英特尔I / O控制器中枢10 [Intel I/O Controller Hub 10]
分类和应用: 控制器
文件页数/大小: 840 页 / 5889 K
品牌: INTEL [ INTEL ]
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Functional Description  
5.16.12 SGPIO Signals  
The SGPIO signals, in accordance to the SFF-8485 specification, support per-port LED  
signaling. These signals are not related to SATALED#, which allows for simplified  
indication of SATA command activity. The SGPIO group interfaces with an external  
controller chip that fetches and serializes the data for driving across the SGPIO bus.  
The output signals then control the LEDs. This feature is only valid in AHCI/RAID mode.  
5.16.12.1 Mechanism  
The enclosure management for SATA Controller 1 (Device 31: Function 2) involves  
sending messages that control LEDs in the enclosure. The messages for this function  
are stored after the normal registers in the AHCI BAR, at Offset 400h bytes for ICH10  
from the beginning of the AHCI BAR as specified by the EM_LOC global register  
(Section 14.4.1.8).  
Software creates messages for transmission in the enclosure management message  
buffer. The data in the message buffer should not be changed if CTL.TM bit is set by  
software to transmit an update message. Software should only update the message  
buffer when CTL.TM bit is cleared by hardware otherwise the message transmitted will  
be indeterminate. Software then writes a register to cause hardware to transmit the  
message or take appropriate action based on the message content. The software  
should only create message types supported by the controller, which is LED messages  
for ICH10. If the software creates other non LED message types (e.g. SAF-TE, SES-2),  
the SGPIO interface may hang and the result is indeterminate.  
During reset all SGPIO pins will be in tri-state state. The interface will continue to be in  
tri-state state after reset until the first transmission occurs when software programs  
the message buffer and sets the transmit bit CTL.TM. The SATA Host controller will  
initiate the transmission by driving SCLOCK and at the same time drive the SLOAD to  
‘0’ prior to the actual bit stream transmission. The Host will drive SLOAD low for at  
least 5 SCLOCK then only start the bit stream by driving the SLOAD to high. SLOAD will  
be driven high for 1 SCLOCK follow by vendor specific pattern that is default to “0000”  
if software has yet to program the value. A total of 18-bit stream from 6 ports (Port0,  
Port1, Port2, Port3, Port4 and Port5) of 3-bit per port LED message will be transmitted  
on SDATAOUT0 pin after the SLOAD is driven high for 1 SCLOCK. Only 2 ports (port4  
and port5) of 6 bit total LED message follow by 12 bits of tri-state value will be  
transmitted out on SDATAOUT1 pin.  
All the default LED message values will be high prior to software setting them, except  
the Activity LED message that is configured to be hardware driven that will be  
generated based on the activity from the respective port. All the LED message values  
will be driven to ‘1’ for the port that is unimplemented as indicated in the Port  
Implemented register regardless of the software programmed value through the  
message buffer.  
There are 2 different ways of resetting ICH SGPIO interface, asynchronous reset and  
synchronous reset. Asynchronous reset is caused by platform reset to cause the SGPIO  
interface to be tri-state asynchronously. Synchronous reset is caused by setting the  
CTL.RESET bit, clearing the GHC.AE bit or HBA reset, where Host Controller will  
complete the existing full bit stream transmission then only tri-state all the SGPIO pins.  
After the reset, both synchronous and asynchronous, the SGPIO pins will stay tri-  
stated.  
Note:  
ICH Host Controller does not ensure to cause the target SGPIO device or controller to  
be reset. Software is responsible to keep ICH SGPIO interface in tri-state stated for 2  
second in order to cause a reset on the target of the SGPIO interface.  
Datasheet  
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