Functional Description
5.16.9
SATA LED
The SATALED# output is driven whenever the BSY bit is set in any SATA port. The
SATALED# is an active-low open-drain output. When SATALED# is low, the LED should
be active. When SATALED# is high, the LED should be inactive.
5.16.10 AHCI Operation
The ICH10 provides hardware support for Advanced Host Controller Interface (AHCI), a
programming interface for SATA host controllers developed through a joint industry
effort. AHCI defines transactions between the SATA controller and software and enables
advanced performance and usability with SATA. Platforms supporting AHCI may take
advantage of performance features such as no master/slave designation for SATA
devices—each device is treated as a master—and hardware assisted native command
queuing. AHCI also provides usability enhancements such as Hot-Plug. AHCI requires
appropriate software support (e.g., an AHCI driver) and for some features, hardware
support in the SATA device or additional platform hardware.
The ICH10 supports all of the mandatory features of the Serial ATA Advanced Host
Controller Interface Specification, Revision 1.2 and many optional features, such as
hardware assisted native command queuing, aggressive power management, LED
indicator support, and Hot-Plug through the use of interlock switch support (additional
platform hardware and software may be required depending upon the implementation).
Note:
For reliable device removal notification while in AHCI operation without the use of
interlock switches (surprise removal), interface power management should be disabled
for the associated port. See Section 7.3.1 of the AHCI Specification for more
information.
5.16.11 Serial ATA Reference Clock Low Power Request
(SATACLKREQ#)
The 100 MHz Serial ATA Reference Clock (SATACLKP, SATACLKN) is implemented on the
system as a ground-terminated low-voltage differential signal pair driven by the system
Clock Chip. When all the SATA links are in Slumber or disabled, the SATA Reference
Clock is not needed and may be stopped and tri-stated at the clock chip allowing
system-level power reductions.
The ICH10 uses the SATACLKREQ# output signal to communicate with the system
Clock Chip to request either SATA clock running or to tell the system clock chip that it
can stop the SATA Reference Clock. ICH10 drives this signal low to request clock
running, and tristates the signal to indicate that the SATA Reference Clock may be
stopped (the ICH10 never drives the pin high). When the SATACLKREQ# is tristated by
the ICH10, the clock chip may stop the SATA Reference Clock within 100 ns, anytime
after 100 ns, or not at all. If the SATA Reference Clock is not already running, it will
start within 100 ns after a SATACLKREQ# is driven low by the ICH10.
To enable SATA Reference Clock Low Power Request:
1. Configure GPIO35 to native function
2. Set SATA Clock Request Enable (SCRE) bit to ‘1’ (Dev 31:F2:Offset 94h:bit 28).
Note:
The reset default for SATACLKREQ# is low to insure that the SATA Reference Clock is
running after system reset.
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Datasheet
INTEL [ INTEL ]
