Intel
®
82598 10 GbE Controller
Revisions
Rev
Date
Comments
• First integrated version.
• Added MUSIC and iSCSI TSO definition.
• Initialization chapter updated
• All main functions are integrated.
Chapters that are not updated:
• NVM memory Map.
• Manageability.
• Power management.
First full version. Too many changes to list here… Revision control indicates changes from
Zoar.
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Pin changes to support 4 more SDP (per port), POR Baypass, Clock Bypass, power pin
changes and number of Spares.
PCIe* read request size is limited to 256B
Removal of PCIe* Gen 2 support
Updated the initialization sequence for proper link setup at the different modes of
network interface
Sync up with Zoar C-spec 0.94
Many address changes in the programming interface
Ball out updated
Added Cibolo for the feature summary comparison
Changes in LAN/SAN use of RSS
Music chapter was updated, registers and statistics related to Music were updated
Added EEPROM to CSR capability
Link initialization was updated
Modified the Tx descriptors to be 8 per queue (instead of 4 and no global descriptors)
Added 10 general purpose semaphores
EEPORM PCIe* fields were re-organized, Added EEPROM words for MAC, Music
Jumbo frame support up to 16KB
Address changes in programming interface
0.75
08/05
0.89
10/05
0.9
11/05
Reference Number: 319282-007
Revision Number: 3.2
October 2010
Intel
®
82598 10 GbE Controller
Datasheet
3
INTEL [ INTEL CORPORATION ]
