Functional Description
10.8
Clocking
The GMCH has a total of 5 PLLs providing many times that many internal clocks. The
PLLs are:
•
Host PLL – Generates the main core clocks in the host clock domain. This PLL can
also be used to generate memory and internal graphics core clocks. The PLL uses
the Host clock (H_CLKIN) as a reference.
•
Memory I/O PLL - Optionally generates low jitter clocks for memory I/O interface,
as opposed to from Host PLL. The PLL uses the Host FSB differential clock
(HPL_CLKINP/HPL_CLKINN) as a reference. Low jitter clock source from Memory
I/O PLL is required for DDR667 and higher frequencies.
•
PCI Express PLL – Generates all PCI Express related clocks, including the Direct
Media , that connect to the ICH. This PLL uses the 100 MHz clock (G_CLKIN) as a
reference.
•
•
•
Display PLL A – Generates the internal clocks for Display A. This PLL uses
D_REFCLKIN as a reference.
Display PLL B – Generates the internal clocks for Display B. This PLL uses
D_REFCLKIN as a reference.
CK505 is the Clocking chip required for the Intel G35 Express Chipset platform
Datasheet
307
INTEL [ INTEL ]
