Clocking
Figure 8-1. AMB Clock Domains
10/17/03
Gold Bridge Block DIagram
AMB Block Diagram
SOUTH
10x2
10x2
NORTH
Southbound
Data In
Southbound
Data Out
Data M erge
2x CA DDR
Re-Tim e
1x DDR/Core
2x DDR + 2xbar
Re-synch
PLL
1x2
Reference Clock
1x Rd DDR
1x fixed/
HVM
4 phases of 6x
FBD
PISO
demux
10*12
Frame
clks and
state
State
and
control
RefClk
10*12
Reset#
Reset
Control
mux
Link Init SM
and Control
Reset
s
Init
patterns
SB Link
CSR’s
4
4
IBIST/DFX -
TX
DRAM Clock
IBIST/DFX - RX
D SET
Q
failover
SBLAI Buffer
2 deep x 120
DRAM Clock #
LAI data
CLR Q
LAI Match and
Mask
Command
Decoder &
CRC Check
DRAM
Cmd
29
29
Cmd Out
DRAM Address /
Command Copy1
D
SET Q
Thermal
Sensor
Q
CLR
DRAM Address /
Command Copy2
DDR
DDR State
Link
Controller
CSR’s
LAI data
Core Control:
NB/SB Combined Init
Reset control
CSR chain control
Data Out
DSET
Q
Internal debug control
36
deep
Q
CLR
72 + 18x2
Write
Data
FIFO
DRAM
Data / Strobe
External MEMBIST
DDRCalibration &
DDR IOBIST/DFX
Data In
Q SET
D
Q
Data CRC Ge n
CLR
& Read FIFO
Sync & Idle
Pattern
Generator
NB LAI Buffer
1 deep x 168
LAI data
IBIST/DFX -
RX
IBIST/DFX -
TX
Init Patterns
mux
Link Init SM
and Control
NB Link
CSR’s
failover
State
and
control
Frame
clks and
state
14*12
demux
14*6*2
PISO
LAI
Controller
5
5
SMBus
JTAG
SMbus
Controller
Re-synch
Re-Tim e
JTAG
Controller
Data Merge
Northbound
Data In
Northbound
Data Out
14x2
14x2
84
Intel® 6400/6402 Advanced Memory Buffer Datasheet
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