SMBus Interface
This is not a problem since SMBus accesses are only required prior to initial link turn-on
or for diagnostic access when a link can not be initialized. It is the host’s responsibility
to monitor for SMBus transactions during a fast reset and retry these transactions when
the link is stable.
An interrupted transaction will result in the AMB as slave not properly acknowledging
the Master. This protects write transactions. However, if a read transaction has
proceeded to the point where the slave no longer acknowledges the master, read data
can be lost when the SMBus state machine is reset. If PEC is enabled, this data loss will
be detected as a PEC error.
The host restricting usage of SMBus to when the link is idle or monitoring “fast resets”
and retrying transactions that are interrupted is the safest SMBus access method.
7.1.5.2
SMBus Interface State Machine Reset
The slave interface state machine can be reset by the master in two ways:
• The master holds SCL low for 25 ms cumulative. Cumulative in this case means
that all the “low time” for SCL is counted between the Start and Stop bit. If this
totals 25 ms before reaching the Stop bit, the interface is reset.
— Timing is set up to be:
* 30 ms at DDR2-667
* 37.5 ms at DDR2-533
• The master holds SCL continuously high for 50 µs.
— Timing is set up to be:
* 60 µs at DDR2-667
* 75 µs at DDR2-533
7.1.5.3
SMBus Transactions During Hard Reset
Since the configuration registers are affected by the reset pin, SMBus masters will NOT
be able to access the internal registers while the system is reset.
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Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
