欢迎访问ic37.com |
会员登录 免费注册
发布采购

313072-002 参数 Datasheet PDF下载

313072-002图片预览
型号: 313072-002
PDF下载: 下载PDF文件 查看货源
内容描述: 高级内存缓冲器 [Advanced Memory Buffer]
分类和应用:
文件页数/大小: 250 页 / 3863 K
品牌: INTEL [ INTEL ]
 浏览型号313072-002的Datasheet PDF文件第84页浏览型号313072-002的Datasheet PDF文件第85页浏览型号313072-002的Datasheet PDF文件第86页浏览型号313072-002的Datasheet PDF文件第87页浏览型号313072-002的Datasheet PDF文件第89页浏览型号313072-002的Datasheet PDF文件第90页浏览型号313072-002的Datasheet PDF文件第91页浏览型号313072-002的Datasheet PDF文件第92页  
Clocking  
8.10.4  
Spread Spectrum Support  
The AMB PLL will support Spread Spectrum Clocking (SSC). SSC is a frequency  
modulation technique for EMI reduction. Instead of maintaining a constant frequency,  
SSC modulates the clock frequency/period along a modulation profile.The AMB is  
designed to support a nominal modulation frequency of 30-33 kHz with a downspread  
of 0.5%.  
See the High Speed Differential Point-to-Point Link at 1.5 V for Fully Buffered DIMM  
Specification and the Circuit Architecture Specifications for the DDR, FBD and PLL  
custom I/Os for more details.  
8.10.5  
8.10.6  
Frequency of Operation  
The PLL’s support a range of operation that exceeds the AMB’s functional range. This  
allows the AMB to be tested at a higher frequency than the maximum specification to  
provide test guardband. Lower frequencies are supported to allow system debug. The  
PLL will also operate with the REFCLK at 100 MHz during transparent mode testing.  
RESET#  
The externally generated RESET# signal indicates when the core voltage is up and  
reference clocks are stable. The core will use an asserted RESET# to asynchronously  
put the AMB in reset, and to hold the AMB in reset. For details see the reset chapter.  
External clocks dependent on PLL’s are DDR clocks and strobes, and SMBus clock.  
8.10.7  
Other PLL Characteristics  
The PLL VCOs oscillate continually from power-up. At all other times, PLL output  
dividers track the VCO, providing pulses to the clock trees. Logic that does not receive  
an asynchronous reset can thus be reset “synchronously.  
A “locked” PLL will only serve to prove that the feedback loop is continuous. It will not  
prove that the entire clock tree is continuous. The PLL is disabled for leakage test.  
88  
Intel® 6400/6402 Advanced Memory Buffer Datasheet