Electrical Specifications
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1.
3. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
4. V
5. V
is the statistical average of the V measured by the oscilloscope.
Havg
Havg
H
can be measured directly using “Vtop” on Agilent* oscilloscopes and “High” on Tektronix* oscilloscopes.
6. Overshoot is defined as the absolute value of the maximum voltage.
7. Undershoot is defined as the absolute value of the minimum voltage.
8. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum
Falling Edge Ringback.
9. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches. It
includes input threshold hysteresis.
Figure 2-7. Differential Clock Crosspoint Specification
650
600
550
550 mV
500
550 + 0.5 (VHavg - 700)
450
400
250 + 0.5 (VHavg - 700)
350
300
250 mV
250
200
660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850
VHavg (mV)
2.8
PECI DC Specifications
PECI is an Intel proprietary one-wire interface that provides a communication channel
between Intel processors (may also include chipset components in the future) and
external thermal monitoring devices. The processor contains Digital Thermal Sensors
(DTS) distributed throughout die. These sensors are implemented as analog-to-digital
converters calibrated at the factory for reasonable accuracy to provide a digital
representation of relative processor temperature. PECI provides an interface to relay
the highest DTS temperature within a die to external management devices for
thermal/fan speed control. More detailed information is available in the Platform
Environment Control Interface (PECI) Specification.
Table 20.
PECI DC Electrical Limits
Symbol
Definition and Conditions
Input Voltage Range
Min
Max
Units Notes1
Vin
-0.15
VTT
—
V
2
Vhysteresis Hysteresis
0.1 * VTT
V
Vn
Vp
Negative-edge threshold voltage
0.275 * VTT
0.550 * VTT
0.500 * VTT
0.725 * VTT
V
V
Positive-edge threshold voltage
High level output source
(VOH = 0.75 * VTT)
Isource
-6.0
N/A
mA
mA
Low level output sink
(VOL = 0.25 * VTT)
Isink
0.5
1.0
50
3
Ileak+
High impedance state leakage to VTT
N/A
µA
Dual-Core Intel® Xeon® Processor 3000 Series Datasheet
33
INTEL [ INTEL ]
