FAST BOOT BLOCK DATASHEET
5.0 DATA PROTECTION
E
6.0
V
VOLTAGES
PP
The Fast Boot Block flash memory architecture
features hardware-lockable main blocks and two
parameter blocks, so critical code can be kept
secure while other parameter blocks are
programmed or erased as necessary.
Intel’s Fast Boot Block flash memory family
provides in-system programming and erase at
2.7 V–3.6 V
temperature) VPP. For customers requiring fast
programming in their manufacturing environment,
this family of products includes an additional low-
cost, high-performance 12 V programming feature.
(3.0 V–3.6 V
for
automotive
5.1
V
≤ V
for Complete
PP
PPLK
The 12 V VPP mode enhances programming
performance during short period of time typically
found in manufacturing processes; however, it is
not intended for extended use. 12 V may be applied
to VPP during block erase and program operations
for a maximum of 1000 cycles on the main blocks
and 2500 cycles on the parameter blocks. VPP may
be connected to 12 V for a total of 80 hours
maximum. Stressing the device beyond these limits
may cause permanent damage.
Protection
The VPP programming voltage can be held low for
complete write protection of all blocks in the flash
device. When VPP is below VPPLK, any block erase
or program operation will result in a error, prompting
the corresponding status register bit (SR.3) to be
set.
5.2
WP# = V for Block Locking
IL
7.0 POWER CONSUMPTION
The lockable blocks are locked when WP# = VIL;
any block erase or program operation to a locked
block will result in an error, which will be reflected in
the status register. For top configuration, the top
two parameter and all main blocks (blocks #37,
#38, and #0 through 30 for the 16-Mbit, blocks #21,
#22, and #0 through #14 for the 8-Mbit) are
lockable. For the bottom configuration, the bottom
two parameter and all main blocks (blocks #0, #1,
and #8 through #38 for the 16-Mbit, blocks #0, #1,
and #8 through #22 for the 8-Mbit) are lockable.
Unlocked blocks can be programmed or erased
normally (unless VPP is below VPPLK).
While in operation, the flash device consumes
active power. However, Intel Flash devices have
power savings that can significantly reduce overall
system power consumption. The Automatic Power
Savings (APS) feature reduces power consumption
when the device is idle. If CE# is deasserted, the
flash enters its standby mode, where current
consumption is even lower. The combination of
these features minimizes overall memory power
and system power consumption.
7.1
Active Power
5.3
WP# = V for Block Unlocking
IH
With CE# at a logic-low level and RST# at a logic-
high level, the device is in active mode. Active
power is the largest contributor to overall system
power consumption. Minimizing active current has a
profound effect on system power consumption,
especially for battery-operated devices.
WP# controls all block locking and VPP provides
protection against spurious writes. Table 9 defines
the write protection methods.
Table 9. Write Protection Truth Table
Write Protection
VPP
WP#
RST#
Provided
7.2
Automatic Power Savings
X
X
VIL
All Blocks Locked
All Blocks Locked
Automatic Power Savings (APS) provides low-
power operation during active mode, allowing the
flash to put itself into a low current state when not
being accessed. After data is read from the memory
array, the device’s power consumption enters the
APS mode where typical ICC current is comparable
to ICCS. The flash stays in this static state with
outputs valid until a new location is read.
VIL
X
VIH
Lockable
Blocks Locked
≥ VPPLK
≥ VPPLK
26
VIL
VIH
VIH
VIH
All
Blocks Unlocked
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