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28F640L18 参数 Datasheet PDF下载

28F640L18图片预览
型号: 28F640L18
PDF下载: 下载PDF文件 查看货源
内容描述: 的StrataFlash无线存储器 [StrataFlash Wireless Memory]
分类和应用: 存储无线
文件页数/大小: 106 页 / 1700 K
品牌: INTEL [ INTEL ]
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Intel StrataFlash® Wireless Memory (L18)  
4.2.2  
128/0 and 256/0 SCSP Package Signal Descriptions  
Table 2 describes the active signals used on the 128/0 and 256/0 SCSP.  
Table 2.  
Device Signal Descriptions for SCSP (Sheet 1 of 2)  
Symbol  
Type  
Description  
ADDRESS INPUTS: Inputs for all die addresses during read and write operations.  
A[Max:0]  
DQ[15:0]  
Input  
128-Mbit Die: A[Max] = A22  
256-Mbit Die: A[Max] = A23  
DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles, outputs data during read  
cycles. Data signals float when the device or its outputs are deselected. Data is internally latched  
during writes.  
Input/  
Output  
FLASH CHIP ENABLE: Low-true: selects the associated flash memory die. When asserted, flash  
internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the  
associated flash die is deselected, power is reduced to standby levels, data and WAIT outputs are  
placed in high-Z state.  
F1-CE#  
F2-CE#  
F3-CE#  
Input  
F1-CE# selects the flash die.  
F2-CE# and F3-CE# are available on stacked combinations with two or three flash dies else they are  
RFU. They each can be tied high to VCCQ through a 10K-ohm resistor for future design flexibility.  
SRAM CHIP SELECTS: When both SRAM chip selects are asserted, SRAM internal control logic,  
input buffers, decoders, and sense amplifiers are active. When either/both SRAM chip selects are  
deasserted (S-CS1# = V or S-CS2 = V ), the SRAM is deselected and its power is reduced to  
S-CS1#  
S-CS2  
Input  
Input  
IH  
IL  
standby levels.  
Treat this signal as NC (No Connect) for this device.  
PSRAM CHIP SELECT: Low-true; when asserted, PSRAM internal control logic, input buffers,  
decoders, and sense amplifiers are active. When deasserted, the PSRAM is deselected and its power  
is reduced to standby levels.  
P-CS#  
Treat this signal as NC (No Connect) for this device.  
FLASH OUTPUT ENABLE: Low-true; enables the flash output buffers. OE#-high disables the flash  
output buffers, and places the flash outputs in High-Z.  
F1-OE#  
F2-OE#  
Input  
Input  
F1-OE# controls the outputs of the flash die.  
F2-OE# is available on stacked combinations with two or three flash dies else it is RFU. It can be  
pulled high to VCCQ through a 10K-ohm resistor for future design flexibility.  
RAM OUTPUT ENABLE: Low-true; R-OE#-low enables the selected RAM output buffers. R-OE#-high  
disables the RAM output buffers, and places the selected RAM outputs in High-Z.  
R-OE#  
Treat this signal as NC (No Connect) for this device.  
FLASH WRITE ENABLE: Low-true; WE# controls writes to the selected flash die. Address and data  
are latched on the rising edge of WE#.  
WE#  
Input  
Input  
RAM WRITE ENABLE: Low-true; R-WE# controls writes to the selected RAM die.  
R-WE#  
Treat this signal as NC (No Connect) for this device.  
FLASH CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode  
and increments the internal address generator. During synchronous read operations, addresses are  
latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs  
first.  
CLK  
Input  
FLASH WAIT: Indicates data valid in synchronous array or non-array burst reads. Configuration  
Register bit 10 (RCR[10], WT) determines its polarity when asserted. With CE# and OE# at V ,  
IL  
WAIT’s active output is V or V when CE# and OE# are asserted. WAIT is high-Z if CE# or OE# is  
OL  
OH  
V
.
IH  
WAIT  
Output  
In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and  
valid data when deasserted.  
In asynchronous page mode, and all write modes, WAIT is deasserted.  
Datasheet  
Intel StrataFlash® Wireless Memory (L18)  
Order Number: 251902, Revision: 009  
April 2005  
21