Intel StrataFlash® Wireless Memory (L18)
Table 2.
Device Signal Descriptions for SCSP (Sheet 2 of 2)
FLASH WRITE PROTECT: Low-true; WP# enables/disables the lock-down protection mechanism of
the selected flash die. WP#-low enables the lock-down mechanism - locked down blocks cannot be
unlocked with software commands. WP#-high disables the lock-down mechanism, allowing locked
down blocks to be unlocked with software commands.
WP#
Input
FLASH ADDRESS VALID: Active-low input. During synchronous read operations, addresses are
latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs
first.
ADV#
Input
In asynchronous mode, the address is latched when ADV# going high or continuously flows through if
ADV# is held low.
RAM UPPER / LOWER BYTE ENABLES: Low-true; During RAM reads, R-UB#-low enables the RAM
high order bytes on DQ[15:8], and R-LB#-low enables the RAM low-order bytes on DQ[7:0].
R-UB#
R-LB#
Input
Input
Input
Treat this signal as NC (No Connect) for this device.
FLASH RESET: Low-true; RST#-low initializes flash internal circuitry and disables flash operations.
RST#-high enables flash operation. Exit from reset places the flash in asynchronous read array mode.
RST#
PSRAM MODE: Low-true; P-MODE is used to program the configuration register, and enter/exit low
power mode.
P-Mode
Treat this signal as NC (No Connect) for this device.
Flash Program/Erase Power: A valid voltage on this pin allows erasing or programming. Memory
contents cannot be altered when V ≤ V
. Block erase and program at invalid V voltages should
PP
PPLK
PP
not be attempted.
Set V = V for in-system program and erase operations. To accommodate resistor or diode drops
PP
CC
VPP,
from the system supply, the V level of V can be as low as V
min. V must remain above
Power/
Input
IH
PP
PPL PP
V
min to perform in-system flash modification. VPP may be 0 V during read operations.
PPL
VPEN
V
can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500
PPH
cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of
this pin at 9 V may reduce block cycling capability.
VPEN (Erase/Program/Block Lock Enables) is not available for L18 products.
Flash Logic Power: F1-VCC supplies power to the core logic of flash die #1; F2-VCC supplies power
F1-VCC
F2-VCC
Power
to the core logic of flash die #2. Write operations are inhibited when V ≤ V
. Device operations at
CC
LKO
invalid V voltages should not be attempted.
CC
SRAM Power Supply: Supplies power for SRAM operations.
S-VCC
P-VCC
Power
Power
Treat this signal as NC (No Connect) for this device.
PSRAM Power Supply: Supplies power for PSRAM operations.
Treat this signal as NC (No Connect) for this device.
VCCQ
VSS
Power
Power
Flash I/O Power: Supply power for the input and output buffers.
Ground: Connect to system ground. Do not float any VSS connection.
Reserved for Future Use: Reserve for future device functionality/ enhancements. Contact Intel
regarding their future use.
RFU
—
DU
NC
—
—
Do Not Use: Do not connect to any other signal, or power supply; must be left floating.
No Connect: No internal connection; can be driven or floated.
April 2005
22
Intel StrataFlash® Wireless Memory (L18)
Order Number: 251902, Revision: 009
Datasheet
INTEL [ INTEL ]
