E
SMART 3 ADVANCED BOOT BLOCK
A Read Array command can now be written to the
CUI to read data from blocks other than that which
is suspended. The only other valid commands while
program is suspended, are Read Status Register,
Read Identifier, and Program Resume. After the
Program Resume command is written to the flash
memory, the WSM will continue with the program
process and status register bits SR.2 and SR.7 will
automatically be cleared. After the Program
Resume command is written, the device
automatically outputs status register data when
read (see Appendix F for Program Suspend and
Resume Flowchart). VPP must remain at the same
VPP level used for program while in program
suspend mode. RP# must also remain at VIH.
After an erase operation, clear the status register
(50H) before attempting the next operation. Any
CUI instruction can follow after erasure is
completed; however, to prevent inadvertent status
register reads, it is advisable to place the flash in
read array mode after the erase is complete.
3.2.5.1
Suspending and Resuming Erase
Since an erase operation requires on the order of
seconds to complete, an Erase Suspend command
is provided to allow erase-sequence interruption in
order to read data from or program data to another
block in memory. Once the erase sequence is
started, writing the Erase Suspend command to the
CUI requests that the WSM pause the erase
sequence at a predetermined point in the erase
algorithm. The status register will indicate if/when
the erase operation has been suspended.
3.2.5
ERASE MODE
To erase a block, write the Erase Set-up and Erase
Confirm commands to the CUI, along with an
address identifying the block to be erased. This
address is latched internally when the Erase
Confirm command is issued. Block erasure results
in all bits within the block being set to “1.” Only one
block can be erased at a time. The WSM will
execute a sequence of internally-timed events to
program all bits within the block to “0,” erase all bits
within the block to “1,” then verify that all bits within
the block are sufficiently erased. While the erase
executes, status bit 7 is a “0.”
A Read Array/Program command can now be
written to the CUI in order to read data from/
program data to blocks other than the one currently
suspended.
The
Program
command
can
subsequently be suspended to read yet another
array location. The only valid commands while
erase is suspended are Erase Resume, Program,
Read Array, Read Status Register, or Read
Identifier. During erase suspend mode, the chip can
be placed in a pseudo-standby mode by taking CE#
to VIH. This reduces active current consumption.
When the status register indicates that erasure is
complete, check the erase status bit to verify that
the erase operation was successful. If the erase
operation was unsuccessful, SR.5 of the status
register will be set to a “1,” indicating an erase
failure. If VPP was not within acceptable limits after
the Erase Confirm command was issued, the WSM
will not execute the erase sequence; instead, SR.5
of the status register is set to indicate an erase
error, and SR.3 is set to a “1” to identify that VPP
supply voltage was not within acceptable limits.
Erase Resume continues the erase sequence when
CE# = VIL. As with the end of a standard erase
operation, the status register must be read and
cleared before the next instruction is issued.
17
PRELIMINARY
INTEL [ INTEL ]
