E
28F016SV FlashFile™ MEMORY
operation) is required from RP# switching high
until outputs are again valid. In the Deep Power-
Down state, the WSM is reset (any current
operation will abort) and the CSR, GSR and BSR
registers are cleared.
A CMOS standby mode of operation is enabled
when either CE
0
# or CE
1
# transitions high and
RP# stays high with all input control pins at CMOS
levels. In this mode, the device typically draws an
I
CC
standby current of 70 µA at 5V V
CC
.
The 28F016SV will be available in 56-lead,
1.2 mm thick, 14 mm x 20 mm TSOP and 56-lead,
1.8 mm thick, 16 mm x 23.7 SSOP Type I
packages. The form factor and pinout of these two
packages allow for very high board layout
densities.
order address and address A
0
is not used (don’t
care). A device block diagram is shown in Figure
1.
The 28F016SV is specified for a maximum access
time of 65 ns (t
ACC
) at 5V operation (4.75V to
5.25V) over the commercial temperature range
(0°C to +70°C). A corresponding maximum access
time of 75 ns at 3.3V (3.0V to 3.6V and 0°C to
+70°C) is achieved for reduced power
consumption applications.
The 28F016SV incorporates an Automatic Power
Saving (APS) feature, which substantially reduces
the active current when the device is in static
mode of operation (addresses not switching). In
APS mode, the typical I
CC
current is 1 mA at 5V
(3.0 mA at 3.3V).
A deep power-down mode of operation is invoked
when the RP# (called PWD# on the 28F008SA)
pin transitions low. This mode brings the device
power consumption to less than 2.0 µA, typically,
and provides additional program protection by
acting as a device reset pin during power
transitions. A reset time of 400 ns (5V V
CC
2.0 DEVICE PINOUT
The 28F016SV 56-lead TSOP and 56-lead SSOP
Type I pinout configurations are shown in Figures
2 and 3.
9
INTEL [ INTEL CORPORATION ]
