E
28F016SV FlashFile™ MEMORY
The implementation of a new architecture, with
many enhanced features, will improve the device
operating characteristics and result in greater
product reliability and ease-of-use.
The 28F016SV
incorporates
SmartVoltage
technology, providing V
CC
operation at both 3.3V
and 5V and program and erase capability at V
PP
=
12V or 5V. Operating at V
CC
= 3.3V, the
28F016SV consumes approximately one half the
power consumption at 5V V
CC
, while 5V V
CC
provides the highest read performance capability.
V
PP
= 5V operation eliminates the need for a
separate 12V converter, while V
PP
= 12V
maximizes
program/erase
performance.
In
addition to the flexible program and erase
voltages, the dedicated V
PP
gives complete code
protection with V
PP
≤
V
PPLK
.
A 3/5# input pin configures the device’s internal
circuitry for optimal 3.3V or 5V read/program
operation.
A Command User Interface (CUI) serves as the
system interface between the microprocessor or
microcontroller and the internal memory operation.
Internal Algorithm Automation allows byte/word
programs and block erase operations to be
executed using a Two-Program command
sequence to the CUI in the same way as the
28F008SA 8-Mbit FlashFile™ memory.
A super-set of commands has been added to the
basic 28F008SA command-set to achieve higher
program performance and provide additional
capabilities. These new commands and features
include:
•
Page Buffer Programs to Flash
•
Command Queuing Capability
•
Automatic Data Programs during Erase
•
Software Locking of Memory Blocks
•
Two-Byte
Systems
Successive
Programs
in
8-bit
1.0 INTRODUCTION
The documentation of the Intel 28F016SV memory
device includes this datasheet, a detailed user’s
manual, and a number of application notes and
design tools, all of which are referenced in
Appendix B.
The datasheet is intended to give an overview of
the chip feature-set and of the operating AC/DC
specifications. The
16-Mbit Flash Product Family
User’s Manual
provides complete descriptions of
the user modes, system interface examples and
detailed descriptions of all principles of operation.
It also contains the full list of software algorithm
flowcharts, and a brief section on compatibility
with the Intel 28F008SA.
A significant 28F016SV change occurred between
datasheet revisions 290528-003 and 290528-004.
This change centers around the addition of a 3/5#
pin to the device’s pinout configuration. Figures 2
and 3 show the 3/5# pin assignment for TSOP and
SSOP Type 1 packages. Intel recommends that all
customers obtain the latest revisions of 28F016SV
documentation.
1.1 Enhanced Features
The 28F016SV is backwards compatible with the
28F016SA and offers the following enhancements:
•
SmartVoltage Technology
Selectable 5V or 12V V
PP
•
V
PP
Level Bit in Block Status Register
•
Additional RY/BY# Configuration
Pulse-On-Program/Erase
•
Additional Upload Device Information
Command Feedback
Device Proliferation Code
Device Configuration Code
1.2 Product Overview
The 28F016SV is a high-performance, 16-Mbit
(16,777,216-bit) block erasable, nonvolatile
random access memory, organized as either
1 Mword x 16 or 2 Mbyte x 8. The 28F016SV
includes thirty-two 64-KB (65,536 byte) blocks or
thirty-two 32-KW (32,768 word) blocks. A chip
memory map is shown in Figure 4.
•
Erase All Unlocked Blocks
Writing of memory data is performed in either byte
or word increments typically within 6 µs
(12V V
PP
)—a 33% improvement over the
28F008SA. A block erase operation erases one of
the 32 blocks in typically 0.6 sec (12V V
PP
),
independent of the other blocks, which is about a
65% improvement over the 28F008SA.
7
INTEL [ INTEL CORPORATION ]
