Contents
8.1.31 LINT[1:0] (I - 1.5 V Tolerant)..................................................................................74
8.1.32 LOCK# (I/O - AGTL) ..............................................................................................75
8.1.33 NCTRL (I - Analog) ................................................................................................75
8.1.34 NMI (I - 1.5 V Tolerant) ..........................................................................................75
8.1.35 PICCLK (I – 2.0 V Tolerant)...................................................................................75
8.1.36 PICD[1:0] (I/O - 1.5 V Tolerant Open-drain) ..........................................................75
8.1.37 PLL1, PLL2 (Analog) .............................................................................................75
8.1.38 PRDY# (O - AGTL) ................................................................................................76
8.1.39 PREQ# (I - 1.5 V Tolerant) ....................................................................................76
8.1.40 PWRGOOD (I – 1.8 V Tolerant).............................................................................76
8.1.41 REQ[4:0]# (I/O - AGTL) .........................................................................................76
8.1.42 RESET# (I - AGTL)................................................................................................76
8.1.43 RP# (I/O - AGTL)...................................................................................................77
8.1.44 RS[2:0]# (I/O - AGTL) ............................................................................................77
8.1.45 RSP# (I - AGTL) ....................................................................................................77
8.1.46 RTTIMPEDP (I-Analog) .........................................................................................77
8.1.47 SMI# (I - 1.5 V Tolerant) ........................................................................................77
8.1.48 STPCLK# (I - 1.5 V Tolerant).................................................................................77
8.1.49 TCK (I - 1.5 V Tolerant) .........................................................................................78
8.1.50 TDI (I - 1.5 V Tolerant)...........................................................................................78
8.1.51 TDO (O - 1.5 V Tolerant Open-drain) ....................................................................78
8.1.52 TESTHI[2:1] (I - 1.25 V Tolerant)...........................................................................78
8.1.53 TESTLO[2:1] (I - 1.5 V Tolerant)............................................................................78
8.1.54 THERMDA, THERMDC (Analog)...........................................................................78
8.1.55 TMS (I - 1.5 V Tolerant) .........................................................................................78
8.1.56 TRDY# (I/O - AGTL) ..............................................................................................78
8.1.57 TRST# (I - 1.5 V Tolerant) .....................................................................................78
8.1.58 VID[4:0] (O – Open-drain)......................................................................................79
8.1.59 V
(Analog) ........................................................................................................79
REF
8.1.60 VTTPWRGD (I – 1.25 V) .......................................................................................79
Signal Summaries...............................................................................................................79
8.2
Figures
1
2
3
4
5
6
7
8
9
Clock Control States...................................................................................................................15
PLL RLC Filter ............................................................................................................................23
PLL Filter Specifications .............................................................................................................24
VTTPWRGD System-Level Connections ...................................................................................27
Noise Estimation.........................................................................................................................28
BCLK (Single Ended)/PICCLK/TCK Generic Clock Timing Waveform.......................................39
Differential BCLK/BCLK# Waveform (Common Mode) ..............................................................39
BCLK/BCLK# Waveform (Differential Mode)..............................................................................40
Valid Delay Timings....................................................................................................................40
10 Setup and Hold Timings .............................................................................................................40
11 Cold/Warm Reset and Configuration Timings ............................................................................41
12 Power-on Sequence and Reset Timings ....................................................................................42
13 Power Down Sequencing and Timings (V
Leading)...............................................................43
CC
14 Power Down Sequencing and Timings (VCCT Leading)............................................................44
15 Test Timings (Boundary Scan) ...................................................................................................45
Datasheet
5
INTEL [ INTEL ]
