Contents
Contents
1.0 Introduction....................................................................................................................................9
1.1
1.2
1.3
1.4
Overview...............................................................................................................................9
State of the Data.................................................................................................................10
Terminology........................................................................................................................10
References .........................................................................................................................10
2.0 Ultra-Low Voltage Intel® Celeron® Processor Features...........................................................13
2.1
New Features in the Ultra-Low Voltage Intel® Celeron® Processor....................................13
2.1.1 100-MHz PSB With AGTL Signaling......................................................................13
2.1.2 256-K On-die Integrated L2 Cache........................................................................13
2.1.3 Data Prefetch Logic ...............................................................................................13
2.1.4 Differential Clocking...............................................................................................13
2.1.5 Signal Differences Between the Mobile Intel® Celeron®
Processor in BGA2 and Micro-PGA2 Packages and
the Ultra-Low Voltage Intel® Celeron® Processor in Micro FC-BGA Packages.....13
Power Management............................................................................................................14
2.2.1 Clock Control Architecture .....................................................................................14
2.2.2 Normal State..........................................................................................................14
2.2.3 Auto Halt State.......................................................................................................14
2.2.4 Quick Start State....................................................................................................15
2.2.5 HALT/Grant Snoop State.......................................................................................16
2.2.6 Deep Sleep State...................................................................................................16
2.2.7 Operating System Implications of Low-power States ............................................16
AGTL Signals......................................................................................................................17
Ultra-Low Voltage Intel® Celeron® Processor CPUID ........................................................17
2.2
2.3
2.4
3.0 Electrical Specifications .............................................................................................................19
3.1
Processor System Signals..................................................................................................19
3.1.1 Power Sequencing Requirements .........................................................................20
3.1.2 Test Access Port (TAP) Connection ......................................................................21
3.1.3 Catastrophic Thermal Protection ...........................................................................21
3.1.4 Unused Signals......................................................................................................21
3.1.5 Signal State in Low-power States..........................................................................21
Power Supply Requirements ..............................................................................................22
3.2.1 Decoupling Guidelines...........................................................................................22
3.2.2 Voltage Planes.......................................................................................................23
3.2.3 PLL RLC Filter Specification..................................................................................23
3.2.4 Voltage Identification .............................................................................................26
3.2.5 VTTPWRGD Signal Quality Specification..............................................................27
System Bus Clock and Processor Clocking........................................................................28
Maximum Ratings ...............................................................................................................29
DC Specifications ...............................................................................................................30
AC Specifications................................................................................................................34
3.6.1 System Bus, Clock, APIC, TAP, CMOS, and Open-drain AC Specifications ........34
3.2
3.3
3.4
3.5
3.6
4.0 System Signal Simulations.........................................................................................................47
4.1
System Bus Clock (BCLK) and PICCLK DC
Datasheet
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INTEL [ INTEL ]
