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253668 参数 Datasheet PDF下载

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型号: 253668
PDF下载: 下载PDF文件 查看货源
内容描述: 双核英特尔​​®至强®处理器 [Dual-Core Intel Xeon Processor]
分类和应用:
文件页数/大小: 104 页 / 3687 K
品牌: INTEL [ INTEL ]
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Signal Definitions  
Table 5-1.  
Signal Definitions (Sheet 7 of 8)  
Name  
Type  
Description  
Notes  
TESTHI[11:0]  
I
TESTHI[11:0] must be connected to a VTT power source through a resistor for proper  
processor operation. Refer to Section 2.6 for TESTHI grouping restrictions.  
THERMDA  
THERMDA2  
Other  
Other  
O
Thermal Diode Anode. THERMDA connects to processor core 0, THERMDA2 connects  
to processor core 1. Refer to the appropriate platform design guidelines for  
implementation details.  
THERMDC  
THERMDC2  
Thermal Diode Cathode. THERMDC connects to processor core 0. THERMDC2  
connects to processor core 1. Refer to the appropriate platform design guidelines for  
implementation details.  
THERMTRIP#  
Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction  
temperature has reached a temperature beyond which permanent silicon damage  
may occur. Measurement of the temperature is accomplished through an internal  
thermal sensor. Upon assertion of THERMTRIP#, the processor will shut off its  
internal clocks (thus halting program execution) in an attempt to reduce the  
1
processor junction temperature. To protect the processor its core voltage (V ) must  
CC  
be removed following the assertion of THERMTRIP#. Intel is currently evaluating  
whether V must also be removed.  
TT  
Driving of the THERMTRIP# signals is enabled within 10 ms of the assertion of  
PWRGOOD and is disabled on de-assertion of PWRGOOD. Once activated,  
THERMTRIP# remains latched until PWRGOOD is de-asserted. While the de-assertion  
of the PWRGOOD signal will de-assert THERMTRIP#, if the processor’s junction  
temperature remains at or above the trip level, THERMTRIP# will again be asserted  
within 10 ms of the assertion of PWRGOOD.  
TMS  
I
I
TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.  
See the eXtended Debug Port: Debug Port Design Guide for UP and DP Platforms for  
further information.  
TRDY#  
TRST#  
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive  
a write or implicit writeback data transfer. TRDY# must connect the appropriate pins  
of all FSB agents.  
I
I
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven  
low during power on Reset.  
V
V
V
provides isolated power for the analog portion of the internal processor core  
CCA  
CCA  
PLL’s. Refer to the appropriate platform design guidelines for complete  
implementation details.  
I
V
provides isolated power for digital portion of the internal processor core  
CCIOPLL  
CCIOPLL  
PLL’s. Follow the guidelines for V  
, and refer to the appropriate platform design  
CCA  
guidelines for complete implementation details.  
VCC_DIE_SENSE  
VCC_DIE_SENSE2  
O
VCC_DIE_SENSE and VCC_DIE_SENSE2 provide an isolated, low impedance  
connection to each processor core power and ground. These signals should be  
connected to the voltage regulator feedback signal, which insures the output voltage  
(that is, processor voltage) remains within specification. Please see the applicable  
platform design guide for implementation details.  
VID[5:0]  
O
VID[5:0] (Voltage ID) pins are used to support automatic selection of power supply  
voltages (V ). These are CMOS signals that are driven by the processor and must be  
CC  
pulled up through a resistor. Conversely, the voltage regulator output must be  
disabled prior to the voltage supply for these pins becomes invalid. The VID pins are  
needed to support processor voltage specification variations. See Table 2-3 for  
definitions of these pins. The VR must supply the voltage that is requested by these  
pins, or disable itself.  
VID_SELECT  
O
O
VID_SELECT is an output from the processor which selects the appropriate VID table  
for the Voltage Regulator. Dual-Core Intel Xeon Processor 5000 series pull this signal  
to ground on the package as this signal is not connected to the processor die.  
VSS_DIE_SENSE  
VSS_DIE_SENSE2  
VSS_DIE_SENSE and VSS_DIE_SENSE2 provide an isolated, low impedance  
connection to each processor core power and ground. These signals should be  
connected to the voltage regulator feedback signal, which insures the output voltage  
(that is, processor voltage) remains within specification. Please see the applicable  
platform design guide for implementation details.  
V
I
V
provides an isolated, internal ground for internal PLL’s. Do not connect directly  
SSA  
SSA  
to ground. This pin is to be connected to V  
circuit.  
and V  
through a discrete filter  
CCA  
CCIOPLL  
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet  
67  
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