Configuration and Low Power Features
The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or
the AutoHALT Powerdown state. See the Intel Architecture Software Developer's Manual, Volume
III: System Programmer's Guide for more information.
The system can generate a STPCLK# while the processor is in the AutoHALT Powerdown state.
When the system deasserts the STPCLK# interrupt, the processor will return execution to the
HALT state.
While in AutoHALT Powerdown state, the processor will process bus snoops.
Figure 35. Clock Control States
SLP# asserted
STPCLK# asserted
Stop
Grant
Normal
Sleep
STPCLK# de-asserted
SLP# de-asserted
STPCLK#
asserted
halt
break
DPSLP#
de-asserted
DPSLP#
asserted
snoop
serviced
HLT
snoop
occurs
STPCLK#
de-asserted
instruction
core voltage raised
snoop
occurs
HALT/
Grant
Snoop
Deeper
Sleep
Deep
Sleep
Auto Halt
snoop
serviced
core voltage lowered
V0001-04
Halt break - A20M#, BINIT#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
7.2.3
Stop-Grant State
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks
after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle.
Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven
(allowing the level to return to VCC) for minimum power drawn by the termination resistors in this
state. In addition, all other input pins on the system bus should be driven to the inactive state.
BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched
and can be serviced by software upon exit from the Stop-Grant state.
RESET# will cause the processor to immediately initialize itself, but the processor will stay in
Stop-Grant state. A transition back to the Normal state will occur with the de-assertion of the
STPCLK# signal. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should
only be de-asserted ten or more bus clocks after the deassertion of SLP#.
A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the
system bus (see Section 7.2.4). A transition to the Sleep state (see Section 7.2.5) will occur with the
assertion of the SLP# signal.
94
Mobile Intel Pentium 4 Processor-M Datasheet
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