Figures
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VCCVID Pin Voltage and Current Requirements................................................15
Typical VCCIOPLL, VCCA and VSSA Power Distribution ..................................17
Phase Lock Loop (PLL) Filter Requirements .....................................................18
Illustration of VCC Static and Transient Tolerances (VID = 1.30 V)....................26
Illustration of VCC Static and Transient Tolerances (VID = 1.20 V)....................28
Illustration of Deep Sleep VCC Static and Transient Tolerances (VID
Setting = 1.30 V) .................................................................................................29
ITPCLKOUT[1:0] Output Buffer Diagram ............................................................34
AC Test Circuit ....................................................................................................41
TCK Clock Waveform..........................................................................................41
Differential Clock Waveform................................................................................42
Differential Clock Crosspoint Specification..........................................................43
System Bus Common Clock Valid Delay Timings...............................................43
System Bus Reset and Configuration Timings....................................................44
Source Synchronous 2X (Address) Timings .......................................................44
Source Synchronous 4X Timings........................................................................45
Power Up Sequence ...........................................................................................46
Power Down Sequence.......................................................................................46
Test Reset Timings .............................................................................................47
THERMTRIP# to Vcc Timing...............................................................................47
FERR#/PBE# Valid Delay Timing .......................................................................47
TAP Valid Delay Timing ......................................................................................48
ITPCLKOUT Valid Delay Timing .........................................................................48
Stop Grant/Sleep/Deep Sleep Timing .................................................................49
Enhanced Intel SpeedStep Technology/Deep Sleep Timing ..............................50
BCLK Signal Integrity Waveform.........................................................................52
Low-to-High System Bus Receiver Ringback Tolerance.....................................53
High-to-Low System Bus Receiver Ringback Tolerance.....................................53
Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP
Buffers.................................................................................................................54
High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP
Buffers.................................................................................................................54
Maximum Acceptable Overshoot/Undershoot Waveform ...................................59
Micro-FCPGA Package Top and Bottom Isometric Views ..................................61
Micro-FCPGA Package Top and Side View........................................................62
Micro-FCPGA Package - Bottom View................................................................64
The Coordinates of the Processor Pins as Viewed From the Top of the
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Package. .............................................................................................................65
Clock Control States............................................................................................94
35
Mobile Intel Pentium 4 Processor-M Datasheet
5
INTEL [ INTEL ]
