Figures
Setting = 1.30 V) ................................................................................................. 29
TCK Clock Waveform.......................................................................................... 41
System Bus Common Clock Valid Delay Timings............................................... 43
System Bus Reset and Configuration Timings....................................................44
Source Synchronous 2X (Address) Timings ....................................................... 44
Source Synchronous 4X Timings ........................................................................ 45
Power Up Sequence ........................................................................................... 46
Power Down Sequence....................................................................................... 46
BCLK Signal Integrity Waveform......................................................................... 52
Buffers ................................................................................................................. 54
Buffers ................................................................................................................. 54
Package. ............................................................................................................. 65
Clock Control States............................................................................................ 94
Mobile Intel
Pentium
4 Processor-M Datasheet
5
INTEL [ INTEL CORPORATION ]
