21150 参数 Datasheet PDF下载

21150

15.2

15.3

16.0

15.1.27 Subsystem Vendor ID Register—Offset 34h........................................ 118

15.1.28 ECP Pointer Register—Offset 34h ....................................................... 118

15.1.29 Subsystem ID Register—Offset 36h .................................................... 119

15.1.30 Interrupt Pin Register—Offset 3Dh....................................................... 119

15.1.31 Bridge Control Register—Offset 3Eh ................................................... 119

15.1.32 Capability ID Register—Offset DCh ..................................................... 122

15.1.33 Next Item Ptr Register—Offset DDh..................................................... 123

15.1.34 Power Management Capabilities Register—Offset DEh ...................... 123

15.1.35 Power Management Control and Status Register—Offset E0h ........... 124

15.1.36 PPB Support Extensions Registers—Offset E2h ................................. 124

15.1.37 Data Register—Offset E3h................................................................... 125

Device-Specific Configuration Registers ........................................................... 125

15.2.1 Chip Control Register—Offset 40h....................................................... 125

15.2.2 Diagnostic Control Register—Offset 41h ............................................. 126

15.2.3 Arbiter Control Register—Offset 42h.................................................... 127

15.2.4 p_serr_l Event Disable Register—Offset 64h....................................... 128

15.2.5 gpio Output Data Register—Offset 65h ............................................... 129

15.2.6 gpio Output Enable Control Register—Offset 66h ............................... 130

15.2.7 gpio Input Data Register—Offset 67h .................................................. 130

15.2.8 Secondary Clock Control Register—Offset 68h ................................... 130

15.2.9 p_serr_l Status Register—Offset 6Ah .................................................. 132

Configuration Register Values After Reset ....................................................... 133

JTAG Test Port .............................................................................................................. 135

16.1

16.2

16.3

16.4

16.5

16.6

Overview ........................................................................................................... 135

JTAG Signal Pins .............................................................................................. 135

Test Access Port Controller .............................................................................. 135

Instruction Register ........................................................................................... 136

Bypass Register ................................................................................................ 136

Boundary-Scan Register ................................................................................... 136

16.6.1 Boundary-Scan Register Cells ............................................................. 137

16.6.2 21150 Boundary-Scan Order ............................................................... 137

Initialization ....................................................................................................... 141

16.7

17.0

Electrical Specifications ................................................................................................. 143

17.1

17.2

17.3

17.4

PCI Electrical Specification Conformance......................................................... 143

Absolute Maximum Ratings .............................................................................. 143

DC Specifications .............................................................................................. 144

AC Timing Specifications .................................................................................. 144

17.4.1 Clock Timing Specifications ................................................................. 145

17.4.2 PCI Signal Timing Specifications ......................................................... 146

17.4.3 Reset Timing Specifications ................................................................. 148

17.4.4 gpio Timing Specifications ................................................................... 149

17.4.5 JTAG Timing Specifications ................................................................. 150

18.0

Mechanical Specifications.............................................................................................. 153

vi

Preliminary

Datasheet