21150
Contents
1.0
Introduction......................................................................................................................... 1
1.1
1.2
1.3
1.4
1.5
2.0
Architecture ........................................................................................................... 3
Data Path .............................................................................................................. 5
Posted Write Queue .............................................................................................. 6
Delayed Transaction Queue.................................................................................. 6
Read Data Queue ................................................................................................. 6
Signal Pins ......................................................................................................................... 7
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Primary PCI Bus Interface Signals ........................................................................ 8
Secondary PCI Bus Interface Signals .................................................................11
Secondary Bus Arbitration Signals......................................................................13
General-Purpose I/O Interface Signals ...............................................................14
Clock Signals.......................................................................................................14
Reset Signals ......................................................................................................15
Miscellaneous Signals.........................................................................................16
JTAG Signals ......................................................................................................17
3.0
Pin Assignments...............................................................................................................19
3.1
3.2
Numeric Pin Assignment .....................................................................................20
Alphabetic Pin Assignment..................................................................................24
4.0
PCI Bus Operation ...........................................................................................................27
4.1
4.2
Types of Transactions .........................................................................................27
Address Phase ....................................................................................................28
4.2.1 Single Address Phase ............................................................................28
4.2.2 Dual Address Phase...............................................................................28
Device Select (DEVSEL#) Generation ................................................................29
Data Phase..........................................................................................................29
Write Transactions ..............................................................................................29
4.5.1 Posted Write Transactions .....................................................................30
4.5.2 Memory Write and Invalidate Transactions ............................................32
4.5.3 Delayed Write Transactions ...................................................................32
4.5.4 Write Transaction Address Boundaries ..................................................34
4.5.5 Buffering Multiple Write Transactions.....................................................35
4.5.6 Fast Back-to-Back Write Transactions ...................................................35
Read Transactions ..............................................................................................36
4.6.1 Prefetchable Read Transactions ............................................................37
4.6.2 Nonprefetchable Read Transactions......................................................37
4.6.3 Read Prefetch Address Boundaries .......................................................38
4.6.4 Delayed Read Requests ........................................................................38
4.6.5 Delayed Read Completion with Target...................................................39
4.6.6 Delayed Read Completion on Initiator Bus ............................................39
Configuration Transactions .................................................................................42
4.7.1 Type 0 Access to the 21150 ...................................................................43
4.7.2 Type 1 to Type 0 Translation..................................................................44
4.7.3 Type 1 to Type 1 Forwarding .................................................................45
4.7.4 Special Cycles ........................................................................................46
4.3
4.4
4.5
4.6
4.7
Preliminary
Datasheet
iii
INTEL [ INTEL CORPORATION ]
