21150
4.8
Transaction Termination ..................................................................................... 47
4.8.1 Master Termination Initiated by the 21150 ............................................. 47
4.8.2 Master Abort Received by the 21150 ..................................................... 48
4.8.3 Target Termination Received by the 21150 ........................................... 50
4.8.3.1 Delayed Write Target Termination Response ........................... 50
4.8.3.2 Posted Write Target Termination Response ............................. 51
4.8.3.3 Delayed Read Target Termination Response ........................... 51
4.8.4 Target Termination Initiated by the 21150 ............................................. 53
4.8.4.1 Target Retry .............................................................................. 53
4.8.4.2 Target Disconnect ..................................................................... 54
4.8.4.3 Target Abort .............................................................................. 54
5.0
Address Decoding............................................................................................................ 55
5.1
5.2
Address Ranges.................................................................................................. 55
I/O Address Decoding ......................................................................................... 55
5.2.1 I/O Base and Limit Address Registers ................................................... 56
5.2.2 ISA Mode ............................................................................................... 57
Memory Address Decoding ................................................................................. 58
5.3.1 Memory-Mapped I/O Base and Limit Address Registers ....................... 59
5.3.2 Prefetchable Memory Base and Limit Address Registers ...................... 60
5.3.3 Prefetchable Memory 64-Bit Addressing Registers................................ 61
VGA Support ....................................................................................................... 62
5.4.1 VGA Mode.............................................................................................. 62
5.4.2 VGA Snoop Mode .................................................................................. 63
5.3
5.4
6.0
Transaction Ordering ....................................................................................................... 65
6.1
6.2
6.3
6.4
Transactions Governed by Ordering Rules ......................................................... 65
General Ordering Guidelines .............................................................................. 66
Ordering Rules .................................................................................................... 66
Data Synchronization .......................................................................................... 68
7.0
Error Handling .................................................................................................................. 69
7.1
7.2
Address Parity Errors .......................................................................................... 69
Data Parity Errors................................................................................................ 70
7.2.1 Configuration Write Transactions to 21150 Configuration Space .......... 70
7.2.2 Read Transactions ................................................................................. 70
7.2.3 Delayed Write Transactions ................................................................... 71
7.2.4 Posted Write Transactions ..................................................................... 73
Data Parity Error Reporting Summary ................................................................ 74
System Error (SERR#) Reporting ....................................................................... 78
7.3
7.4
8.0
Exclusive Access ............................................................................................................. 81
8.1
8.2
8.3
Concurrent Locks ................................................................................................ 81
Acquiring Exclusive Access Across the 21150 ................................................... 81
Ending Exclusive Access .................................................................................... 82
9.0
PCI Bus Arbitration........................................................................................................... 85
9.1
9.2
Primary PCI Bus Arbitration ................................................................................ 85
Secondary PCI Bus Arbitration ........................................................................... 85
9.2.1 Secondary Bus Arbitration Using the Internal Arbiter............................. 85
9.2.2 Secondary Bus Arbitration Using an External Arbiter............................. 87
iv
Preliminary
Datasheet
INTEL [ INTEL CORPORATION ]
