M10-OVERVIEW
2014.09.22
13
Configuration
External Memory Interface(2)
I/O Standard
SSTL-18
Maximum Width
16 bit + 8 bit ECC
16 bit without ECC
Maximum Frequency (MHz)
DDR2 SDRAM
200
200
LPDDR2 SDRAM
HSUL-12
Note: MAX 10 FPGA support for the DDR3, DDR3L, DDR2, and LPDDR2 external memory interfaces is
not available by default in the Quartus II software. Contact your local sales representative for
support.
Related Information
External Memory Interface Spec Estimator
Provides a parametric tool that allows you to find and compare the performance of the supported external
memory interfaces in Altera devices.
Configuration
Table 12: Configuration Features
Feature
Description
Dual-image configuration
•
•
Stores two configuration images in the configuration flash memory
(CFM)
Selects the first configuration image to boot using the BOOT_SEL
pin
Design security
•
•
Supports 128 bit key with non-volatile key programming
Limits access of the JTAG instruction during power-up in the JTAG
secure mode
SEU Mitigation(3)
•
•
Auto-detects cyclic redundancy check (CRC) errors during configu‐
ration
Provides optional CRC error detection and identification in user
mode.
Dual-purpose configuration pin
Configuration data compression
•
•
Functions as configuration pins prior to user mode
Provides option to be used as configuration pins or user I/O pins in
user mode
•
•
Receives compressed configuration bitstream and decompresses the
data in real-time during configuration
Reduces the configuration image size stored in the CFM
(2)
The device hardware supports SRAM. Use your own design to interface with SRAM devices.
The SEU mitigation feature for single supply devices is disabled by default in the Quartus II software. For
more information and support, contact your local sales representative.
(3)
MAX 10 FPGA Device Overview
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