M10-OVERVIEW
2014.09.22
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FPGA General Purpose I/O
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Reduction in the number of oscillators required on the board
Reduction in the device clock pins through multiple clock frequency synthesis from a single reference
clock source
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Frequency synthesis
On-chip clock de-skew
Jitter attenuation
Dynamic phase-shift
Zero delay buffer
Counters reconfiguration
Bandwidth reconfiguration
Programmable output duty cycle
PLL cascading
Reference clock switchover
Driving of the ADC block
FPGA General Purpose I/O
The MAX 10 device I/O buffers support the following programmable features:
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Programmable current strength
Programmable output slew-rate control
Programmable IOE delay
PCI clamp diode
Programmable pre-emphasis
Programmable emulated differential output
Programmable dynamic power down
Programmable bus hold
Programmable weak pull up
Programmable open drain
External Memory Interface
The MAX 10 devices feature one soft memory controller for DDR3, DDR3L, DDR2, and LPDDR2
SDRAM interfaces on the right side of the device. The external memory controller in MAX 10 devices
supports 16 bit SDRAM components with error correction coding (ECC).
The external memory interface feature is available for dual supply MAX 10 devices only.
Table 11: External Memory Interface Performance
External Memory Interface(2)
DDR3 SDRAM
I/O Standard
SSTL-15
Maximum Width
16 bit + 8 bit ECC
16 bit + 8 bit ECC
Maximum Frequency (MHz)
303
303
DDR3L SDRAM
SSTL-135
(2)
The device hardware supports SRAM. Use your own design to interface with SRAM devices.
MAX 10 FPGA Device Overview
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Altera Corporation
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