A10-DATASHEET
2015.12.31
81
JTAG Configuration Timing
Related Information
MSEL Pin Settings
Provides more information about POR delay based on MSEL pin settings for each configuration scheme.
JTAG Configuration Timing
Table 74: JTAG Timing Parameters and Values for Arria 10 Devices—Preliminary
Symbol
Description
Min
Max
—
—
—
—
—
—
11
14
14
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCP
tJCH
tJCL
TCKclock period
30, 167 (93)
TCKclock high time
14
14
2
TCKclock low time
tJPSU (TDI)
tJPSU (TMS)
tJPH
TDIJTAG port setup time
TMSJTAG port setup time
JTAG port hold time
JTAG port clock to output
3
5
tJPCO
—
—
—
tJPZX
JTAG port high impedance to valid output
JTAG port valid output to high impedance
tJPXZ
FPP Configuration Timing
DCLK-to-DATA[] Ratio (r) for FPP Configuration
Fast passive parallel (FPP) configuration requires a different DCLK-to-DATA[]ratio when you turn on encryption or the compression feature.
Depending on the DCLK-to-DATA[]ratio, the host must send a DCLKfrequency that is r times the DATA[]rate in byte per second (Bps) or word per
second (Wps). For example, in FPP ×16 where the r is 2, the DCLKfrequency must be 2 times the DATA[]rate in Wps.
(93)
The minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2 V – 1.5 V when you perform the volatile key programming.
Arria 10 Device Datasheet
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