A10-DATASHEET
2015.12.31
80
GPIO Interface
Figure 25: Trace Timing Diagram
Tclk
D0 - D3 (DDR)
D0
D1
D2
D3
D4
td
td
GPIO Interface
The general-purpose I/O (GPIO) interface has debounce circuitry included to remove signal glitches. The debounce clock frequency ranges from
125 Hz to 32 kHz. The minimum pulse width is 2 debounce clock cycles and the minimum detectable GPIO pulse width is 62.5 us (at 32 kHz). Any
pulses shorter than 2 debounce clock cycles are filtered by the GPIO peripheral.
Configuration Specifications
This section provides configuration specifications and timing for Arria 10 devices.
POR Specifications
Power-on reset (POR) delay is defined as the delay between the time when all the power supplies monitored by the POR circuitry reach the
minimum recommended operating voltage to the time when the nSTATUSis released high and your device is ready to begin configuration.
Table 73: Fast and Standard POR Delay Specification for Arria 10 Devices—Preliminary
POR Delay
Minimum
Maximum
12 (92)
Unit
ms
Fast
4
Standard
100
300
ms
(92)
The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize after the POR trip.
Arria 10 Device Datasheet
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