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10AX115U1F45E1SG 参数 Datasheet PDF下载

10AX115U1F45E1SG图片预览
型号: 10AX115U1F45E1SG
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 1150000-Cell, CMOS, PBGA1932, 45 X 45 MM, ROHS COMPLIANT, FBGA-1932]
分类和应用: 可编程逻辑
文件页数/大小: 110 页 / 1391 K
品牌: INTEL [ INTEL ]
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A10-DATASHEET  
2015.12.31  
85  
AS Configuration Timing  
Symbol  
Parameter  
Minimum  
Maximum  
Unit  
tCD2CU  
CONF_DONEhigh to CLKUSRenabled  
4 × maximum DCLK  
period  
tCD2UMC  
CONF_DONEhigh to user mode with CLKUSRoption on  
tCD2CU  
+
(600 × CLKUSR  
period)  
Related Information  
FPP Configuration Timing  
Provides the FPP configuration timing waveforms.  
AS Configuration Timing  
Table 78: AS Timing Parameters for AS ×1 and AS ×4 Configurations in Arria 10 Devices—Preliminary  
The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.  
The tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for passive serial (PS) mode listed in PS Timing  
Parameters for Arria 10 Devices table.  
Symbol  
Parameter  
Minimum  
Maximum  
Unit  
ns  
tCO  
tSU  
DCLKfalling edge to AS_DATA0/ASDOoutput  
Data setup time before falling edge on DCLK  
Data hold time after falling edge on DCLK  
CONF_DONEhigh to user mode  
1
4
ns  
tDH  
1.5  
175  
ns  
tCD2UM  
tCD2CU  
830  
μs  
CONF_DONEhigh to CLKUSRenabled  
4 × maximum DCLK  
period  
tCD2UMC  
CONF_DONEhigh to user mode with CLKUSRoption on  
tCD2CU + (600 ×  
CLKUSRperiod)  
Related Information  
PS Configuration Timing on page 86  
Arria 10 Device Datasheet  
Send Feedback  
Altera Corporation  
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