A10-DATASHEET
2015.12.31
59
HPS Specifications
Figure 5: Timing Diagram for on oe and dyn_term_ctrl Signals
Tristate
TX
Tristate
RX
RX
oe
dyn_term_ctrl
TRS_RT
TRS_RT
HPS Specifications
This section provides HPS specifications and timing for Arria 10 devices. The specifications are preliminary.
HPS Reset Input Requirements
Table 55: HPS Reset Input Requirements for Arria 10 Devices—Preliminary
Description
Min
600
600
—
Max
—
Unit
HPS cold reset pulse width
ns
HPS warm reset pulse width
—
ns
osc1 clocks
μs
Cold reset deassertion to BSEL sampling, using osc1 clock
1000
100
Cold reset deassertion to BSEL sampling, using secure clock,
without RAM clearing
—
Cold reset deassertion to BSEL sampling, using secure clock, with
RAM clearing
—
50
ms
Arria 10 Device Datasheet
Send Feedback
Altera Corporation
INTEL [ INTEL ]
