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10AX115U1F45E1SG 参数 Datasheet PDF下载

10AX115U1F45E1SG图片预览
型号: 10AX115U1F45E1SG
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 1150000-Cell, CMOS, PBGA1932, 45 X 45 MM, ROHS COMPLIANT, FBGA-1932]
分类和应用: 可编程逻辑
文件页数/大小: 110 页 / 1391 K
品牌: INTEL [ INTEL ]
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A10-DATASHEET  
2015.12.31  
57  
DLL Range Specifications  
DLL Range Specifications  
Table 51: DLL Frequency Range Specifications for Arria 10 Devices—Preliminary  
Arria 10 devices support memory interface frequencies lower than 667 MHz, although the reference clock that feeds the DLL must be at least 667 MHz. To  
support interfaces below 667 MHz, multiply the reference clock feeding the DLL to ensure the frequency is within the supported range.  
Parameter  
Performance (for All Speed Grades)  
Unit  
DLL operating frequency range  
667 – 1333  
MHz  
DQS Logic Block Specifications  
Table 52: DQS Phase Shift Error Specifications for DLL-Delayed Clock (tDQS_PSERR) for Arria 10 Devices—Preliminary  
This error specification is the absolute maximum and minimum error.  
Symbol  
Performance (for All Speed Grades)  
Unit  
tDQS_PSERR  
5
ps  
Arria 10 Device Datasheet  
Send Feedback  
Altera Corporation  
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