A10-DATASHEET
2015.12.31
58
Memory Output Clock Jitter Specifications
Memory Output Clock Jitter Specifications
Table 53: Memory Output Clock Jitter Specifications for Arria 10 Devices—Preliminary
The clock jitter specification applies to the memory output clock pins clocked by an integer PLL, or generated using differential signal-splitter and double
data I/O circuits clocked by a PLL output routed on a PHY clock network as specified. Altera recommends using PHY clock networks for better jitter
performance.
The memory output clock jitter is applicable when an input jitter of 10 ps peak-to-peak is applied with bit error rate (BER) 10–12, equivalent to 14 sigma.
–E1L, –E1M (79), –E1S,
–I1L, –I1M (79), –I1S
–E2L, –E2S, –I2L, –I2S
–E1M (80), –I1M (80), –E3S,
–I3S
Parameter
Clock Network
Symbol
Unit
Min
58
Max
58
Min
58
Max
58
Min
58
Max
58
Clock period jitter
tJIT(per)
tJIT(cc)
ps
ps
ps
PHY
clock
Cycle-to-cycle period jitter
Duty cycle jitter
58
58
58
58
58
58
tJIT(duty)
58
58
58
58
58
58
OCT Calibration Block Specifications
Table 54: OCT Calibration Block Specifications for Arria 10 Devices—Preliminary
Symbol
OCTUSRCLK
TOCTCAL
Description
Min
Typ
—
Max
20
Unit
Clock required by OCT calibration blocks
—
MHz
Number of OCTUSRCLK clock cycles required for
RS OCT /RT OCT calibration
> 2000
—
—
Cycles
TOCTSHIFT
TRS_RT
Number of OCTUSRCLK clock cycles required for OCT
code to shift out
—
—
32
—
—
Cycles
ns
Time required between the dyn_term_ctrland oesignal
transitions in a bidirectional I/O buffer to dynamically
switch between RS OCT and RT OCT
2.5
(79)
(80)
When you power VCC and VCCP at nominal voltage of 0.90 V.
When you power VCC and VCCP at lower voltage of 0.83 V.
Arria 10 Device Datasheet
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