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10AX057H4F34I3SG 参数 Datasheet PDF下载

10AX057H4F34I3SG图片预览
型号: 10AX057H4F34I3SG
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 570000-Cell, CMOS, PBGA1152, 35 X 35 MM, ROHS COMPLIANT, FBGA-1152]
分类和应用: 可编程逻辑
文件页数/大小: 110 页 / 1391 K
品牌: INTEL [ INTEL ]
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A10-DATASHEET  
2015.12.31  
33  
Transceiver Specifications for Arria 10 GX, SX, and GT Devices  
Transceiver Speed Grades 1, 2, 3, 4, and 5  
Symbol/Description  
Condition  
Unit  
Min  
Typ  
600  
700  
700  
Max  
VCCR_GXB = 0.95 V  
VCCR_GXB = 1.03 V  
VCCR_GXB = 1.12 V  
mV  
mV  
mV  
µs  
VICM (AC and DC  
coupled)  
(43)  
tLTR  
10  
(44)  
tLTD  
4
µs  
(45)  
tLTD_manual  
4
µs  
(46)  
tLTR_LTD_manual  
15  
µs  
Run Length  
200  
300  
1000  
UI  
PCIe-only  
-300  
-1000  
PPM  
PPM  
dB  
CDR PPM  
tolerance  
All other protocols  
DC Gain Setting = 0  
DC Gain Setting = 1  
DC Gain Setting = 2  
DC Gain Setting = 3  
DC Gain Setting = 4  
-10  
-6.5  
-3  
dB  
Programmable DC  
Gain  
dB  
0.5  
4
dB  
dB  
(43)  
(44)  
(45)  
tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.  
tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodatasignal goes high.  
tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodatasignal goes high when the CDR is  
functioning in the manual mode.  
tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtorefsignal goes high when the  
CDR is functioning in the manual mode.  
(46)  
Arria 10 Device Datasheet  
Send Feedback  
Altera Corporation  
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