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10AX057H4F34I3SG 参数 Datasheet PDF下载

10AX057H4F34I3SG图片预览
型号: 10AX057H4F34I3SG
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 570000-Cell, CMOS, PBGA1152, 35 X 35 MM, ROHS COMPLIANT, FBGA-1152]
分类和应用: 可编程逻辑
文件页数/大小: 110 页 / 1391 K
品牌: INTEL [ INTEL ]
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A10-DATASHEET  
2015.12.31  
32  
Transceiver Specifications for Arria 10 GX, SX, and GT Devices  
Transceiver Speed Grades 1, 2, 3, 4, and 5  
Typ  
Symbol/Description  
Condition  
Unit  
Min  
Max  
Absolute VMIN for  
a receiver pin (40)  
-0.4  
V
Maximum peak-  
to-peak differen‐  
tial input voltage  
VID (diff p-p)  
1.6  
V
before device  
configuration (41)  
Maximum peak-  
to-peak differen‐  
tial input voltage  
VID (diff p-p) after  
VCCR_GXB = 1.12 V  
VCCR_GXB = 1.03 V  
2.0  
2.0  
V
V
device configura‐ VCCR_GXB = 0.95 V  
2.4  
V
tion (41)  
Minimum  
differential eye  
opening at  
50  
mV  
receiver serial  
input pins (42)  
Differential on-  
chip termination  
resistors  
85-Ω setting  
100-Ω setting  
85 30%  
Ω
Ω
100 30%  
(40)  
The device cannot tolerate prolonged operation at this absolute maximum.  
DC coupling specifications are pending silicon characterization.  
The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver Equaliza‐  
tion, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.  
(41)  
(42)  
Arria 10 Device Datasheet  
Send Feedback  
Altera Corporation  
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