A10-DATASHEET
2015.12.31
100
Document Revision History
Date
Version
Changes
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•
Updated the hmc_free_clk specifications for the following speed grades in HPS Clock Performance for
Arria 10 Devices table:
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–1 speed grade: Updated from 667 MHz to 533 MHz.
–2 speed grade: Updated from 544 MHz to 533 MHz.
Changed from Tsclk to Tclk and added the following specifications in the Quad Serial Peripheral Interface
(SPI) Flash Timing Requirements for Arria 10 Devices table.
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Tqspi_clk
Tdin_start
Tdin_end
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Updated SPI Master Timing Requirements for Arria 10 Devices table.
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Changed the symbol from Tspi_clk to Tclk
Added note to Tdssfrst, Tdsslst, and Th.
Updated note to Tsu.
.
Updated the description for Tsu and Th.
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Updated the note to Tssfsu, Tssfh, Tsslsu, and Tsslh in the SPI Slave Timing Requirements for Arria 10 Devices
table.
Updated the following timing diagrams:
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Quad SPI Flash Serial Output Timing Diagram
SPI Master Output Timing Diagram
SPI Slave Output Timing Diagram
•
Added the following timing diagrams:
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Quad SPI Flash Serial Input Timing Diagram
SPI Master Input Timing Diagram
SPI Slave Input Timing Diagram
Arria 10 Device Datasheet
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