6
Transceiver Power Supply Operating Conditions
A10-DATASHEET
2015.12.31
Symbol
Description
Condition
Minimum
(3)
Typical
Maximum
(3)
Unit
t
RAMP
(10)(11)
Power supply ramp time
Standard POR
Fast POR
200 µs
200 µs
—
—
100 ms
4 ms
—
—
Related Information
on page 17
Transceiver Power Supply Operating Conditions
Table 4: Transceiver Power Supply Operating Conditions for Arria 10 GX/SX Devices—Preliminary
Symbol
Description
Condition
(12)
Minimum
(13)
Typical
Maximum
Unit
Chip-to-Chip ≤ 17.4 Gbps
Or
V
CCT_GXB[L,R]
Transmitter power supply
Backplane
(14)
≤ 16.0 Gbps
Chip-to-Chip ≤ 11.3 Gbps
Or
Backplane
(14)
≤ 10.3125 Gbps
1.0
1.03
1.06
V
0.92
0.95
0.98
V
(3)
(10)
(11)
(12)
(13)
(14)
This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the
PDN tool for the additional budget for the dynamic tolerance requirements.
This is also applicable to HPS power supply. For HPS power supply, refer to t
RAMP
specifications for standard POR when HPS_PORSEL = 0 and
t
RAMP
specifications for fast POR when HPS_PORSEL = 1.
t
ramp
is the ramp time of each individual power supply, not the ramp time of all combined power supplies.
These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Arria 10 GX/SX Devices for exact data
rate ranges.
This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the
PDN tool for the additional budget for the dynamic tolerance requirements.
Backplane applications assume advanced equalization circuitry, such as decision feedback equalization (DFE), is enabled to compensate for signal
impairments. Chip-to-chip links are assumed to be applications with short reach channels that do not require DFE.
Arria 10 Device Datasheet
Altera Corporation
INTEL [ INTEL CORPORATION ]
