A10-DATASHEET
2015.12.31
98
Document Revision History
Document Revision History
Date
Version
Changes
December 2015
2015.12.31
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Updated M20K block specifications for "True dual port, all supported widths" and "ROM, all supported
widths" in the Memory Clock Performance Specifications (VCC and VCCP at 0.9 V Typical Value) table.
Updated maximum resolution from 8 bit 6 bit and added minimum clock frequency of 0.1 MHz in Internal
Voltage Sensor Specifications for Arria 10 Devices table.
Updated the sinusoidal jitter from 0.35 UI to 0.28 UI in LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance
Specifications.
December 2015
November 2015
2015.12.18
2015.11.02
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Changed the minimum specifications in the "Transceiver Power Supply Operating Conditions for Arria 10
GT Devices" table.
Changed conditions in the "Transmitter and Receiver Data Rate Performance" table.
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Added power option V which is supported with the SmartVID feature (lowest static power).
Added note for SmartVID in Recommended Operating Conditions for Arria 10 Devices table. Note:
SmartVID is supported in devices with –2V and –3V speed grades only.
Removed 20-Ω RT in OCT Calibration Accuracy Specifications for Arria 10 Devices table.
Updated specifications in OCT Without Calibration Resistance Tolerance Specifications for Arria 10
Devices table.
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Updated the note for Value column in the Internal Weak Pull-Up Resistor Values for Arria 10 Devices table.
Added Internal Weak Pull-Down Resistor Values for Arria 10 Devices table.
Updated fractional PLL specifications:
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Updated fIN minimum from 50 MHz to 30 MHz and maximum from 1000 MHz to 800 MHz for all
speed grades.
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Updated fINPFD minimum from 50 MHz to 30 MHz and maximum from 325 MHz to 700 MHz.
Updated fVCO minimum from 3.125 GHz to 3.5 GHz and maximum from 6.25 GHz to 7.05 GHz.
Updated tEINDUTY minimum from 40% to 45% and maximum from 60% to 55%.
Removed the conditions for fOUT and fCLBW
.
Updated the descriptions for fDYCONFIGCLK, tLOCK, and tARESET
.
Arria 10 Device Datasheet
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