A10-DATASHEET
2015.12.31
96
Glossary
Term
Definition
Single-ended voltage referenced I/O
standard
The JEDEC standard for the SSTL and HSTL I/O defines both the AC and DC input signal values. The
AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC
values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined.
After the receiver input has crossed the AC value, the receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach
is intended to provide predictable receiver timing in the presence of input waveform ringing.
Single-Ended Voltage Referenced I/O Standard
V CCIO
V OH
V IH(AC)
V IH(DC)
V REF
V IL(DC)
V IL(AC)
V OL
V SS
tC
High-speed receiver/transmitter input and output clock period.
TCCS (channel-to-channel-skew)
The timing difference between the fastest and slowest output edges, including the tCO variation and clock
skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to
the Timing Diagram figure under SW in this table).
tDUTY
High-speed I/O block—Duty cycle on high-speed transmitter output clock.
Signal high-to-low transition time (80–20%)
tFALL
tINCCJ
Cycle-to-cycle jitter tolerance on the PLL clock input
Period jitter on the GPIO driven by a PLL
tOUTPJ_IO
tOUTPJ_DC
Period jitter on the dedicated clock output driven by a PLL
Signal low-to-high transition time (20–80%)
tRISE
Timing Unit Interval (TUI)
The timing budget allowed for skew, propagation delays, and the data sampling window.
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w).
Arria 10 Device Datasheet
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