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10AS066K4F40E3SG 参数 Datasheet PDF下载

10AS066K4F40E3SG图片预览
型号: 10AS066K4F40E3SG
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 660000-Cell, CMOS, PBGA1517, 40 X 40 MM, ROHS COMPLIANT, FBGA-1517]
分类和应用: 可编程逻辑
文件页数/大小: 110 页 / 1391 K
品牌: INTEL [ INTEL ]
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A10-DATASHEET  
2015.12.31  
30  
Transceiver Specifications for Arria 10 GX, SX, and GT Devices  
Transceiver Speed Grades 1, 2, 3, 4, and 5  
Symbol/Description  
Condition  
Unit  
Min  
Typ  
0.95  
1.03  
1.12  
Max  
VCCR_GXB = 0.95 V  
VCCR_GXB = 1.03 V  
VCCR_GXB = 1.12 V  
V
V
VICM (AC coupled)  
V
VICM (DC coupled)  
HCSL I/O standard for  
PCIe reference clock  
250  
550  
mV  
100 Hz  
1 kHz  
–70  
–90  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
ps (rms)  
Transmitter REFCLKPhase Noise (622  
10 kHz  
100 kHz  
≥ 1 MHz  
–100  
–110  
–120  
4.2  
MHz) (38)  
Transmitter REFCLKPhase Jitter (100  
MHz)  
1.5 to 100 MHz (PCIe)  
RREF  
2.0 k 1%  
Ω
TSSC-MAX-PERIOD-SLEW  
Max SSC df/dt  
0.75  
Table 31: Transceiver Clocks Specifications—Preliminary  
Transceiver Speed Grades 1, 2, 3, 4, and 5  
Typ  
Symbol/Description  
Condition  
Unit  
Min  
Max  
CLKUSRpin for  
transceiver  
calibration  
Transceiver  
Calibration  
100  
125  
MHz  
(38)  
To calculate the REFCLKphase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLKphase noise at f (MHz) =  
REFCLKphase noise at 622 MHz + 20*log(f/622).  
Arria 10 Device Datasheet  
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Altera Corporation