A10-DATASHEET
2015.12.31
29
Transceiver Specifications for Arria 10 GX, SX, and GT Devices
Transceiver Specifications for Arria 10 GX, SX, and GT Devices
Table 30: Reference Clock Specifications—Preliminary
Transceiver Speed Grades 1, 2, 3, 4, and 5
Symbol/Description
Condition
Unit
Min
Typ
Max
Dedicated reference clock
pin
CML, Differential LVPECL, LVDS, and HCSL
Supported I/O Standards
RX reference clock pin
CML, Differential LVPECL, and LVDS
Input Reference Clock Frequency (CMU
PLL)
61
100
20
—
—
—
800
800
800
MHz
MHz
MHz
Input Reference Clock Frequency (ATX
PLL)
Input Reference Clock Frequency (fPLL
PLL)
Rise time
Fall time
Duty cycle
20% to 80%
80% to 20%
—
—
—
45
30
—
—
—
—
400
400
55
ps
ps
%
Spread-spectrum modulating clock
frequency
33
kHz
PCIe
Spread-spectrum downspread
On-chip termination resistors
PCIe
—
—
—
—
0 to –0.5
100
—
—
%
Ω
V
Dedicated reference clock
pin
—
1.6
Absolute VMAX
RX reference clock pin
—
—
—
—
1.2
—
V
V
Absolute VMIN
—
—
–0.4
200
Peak-to-peak differential input voltage
1600
mV
Arria 10 Device Datasheet
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