IA8044/IA8344
Data Sheet
SDLC Communications Controller
March 30, 2010
Table 38. Transmit Control Byte Register
7
6
5
4
3
2
1
0
TCB.7 TCB.6 TCB.5 TCB.4 TCB.3 TCB.2 TCB.1 TCB.0
4.10.9 Receive Buffer Start Address Register (RBS)
Table 39 presents the Receive Buffer Start Address Register, which contains the address in
internal RAM where the frame (starting with the I-field) being received is to be stored. The CPU
should write RBS only when the SIU is not receiving a frame, RBE = 0. RBS is byte addressable.
Table 39. Receive Buffer Start Address Register
7
6
5
4
3
2
1
0
RBS.7 RBS.6 RBS.5 RBS.4 RBS.3 RBS.2 RBS.1 RBS.0
4.10.10 Receive Buffer Length Register (RBL)
Table 40 presents the Receive Buffer Length Register, which contains the length, in number of
bytes, of the I-field storage area in internal RAM. RBL = 0 is valid (no I-field). The CPU should
write RBL only when the SIU is not receiving a frame, RBE = 0. The receive buffer will not wrap
around after address 191 (BFH). A buffer end is automatically generated when address 191 is
reached. RBL is byte addressable.
Table 40. Receive Buffer Length Register
7
6
5
4
3
2
1
0
RBL.7 RBL.6 RBL.5 RBL.4 RBL.3 RBL.2 RBL.1 RBL.0
4.10.11 Receive Field Length Register (RFL)
Table 41 presents the Receive Field Length Register, which contains the length, in number of
bytes, of the I-field of the frame received and stored in internal RAM. RFL = 0 is valid (no
I-field). The CPU should access RFL only when the SIU is not receiving a frame, RBE = 0. RFL
is loaded by the SIU. RFL is byte addressable.
Table 41. Receive Field Length Register
7
6
5
4
3
2
1
0
RFL.7 RFL.6 RFL.5 RFL.4 RFL.3 RFL.2 RFL.1 RFL.0
4.10.12 Receive Control Byte Register (RCB)
Table 42 presents the Receive Control Byte Register, which contains the control field of the frame
received and stored in internal RAM. RCB is only readable by the CPU and the CPU should
access RCB only when the SIU is not receiving a frame, RBE = 0. RCB is loaded by the SIU.
RCB is byte addressable.
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