IA8044/IA8344
Data Sheet
SDLC Communications Controller
March 30, 2010
4.10.5 Station Address Register (STAD)
Table 35 presents the Station Address Register, which contains the station address (node address)
of the chip. The CPU can read or write STAD but should access STAD only when RTS = 0 and
RBE = 0. Normally STAD is accessed only during initialization. STAD is byte addressable.
Table 35. Station Address Register
7
6
5
4
3
2
1
0
STAD.7 STAD.6 STAD.5 STAD.4 STAD.3 STAD.2 STAD.1 STAD.0
4.10.6 Transmit Buffer Start Address Register (TBS)
Table 36 presents the Transmit Buffer Start Address Register, which contains the address in
internal RAM where the frame to be transmitted (starting with the I-field) is stored. The CPU
should access TBS only when the SIU is not transmitting a frame, TBF = 0. TBS is byte
addressable.
Table 36. Transmit Buffer Start Address Register
7
6
5
4
3
2
1
0
TBS.7 TBS.6 TBS.5 TBS.4 TBS.3 TBS.2 TBS.1 TBS.0
4.10.7 Transmit Buffer Length Register (TBL)
Table 37 presents the Transmit Buffer Length Register, which contains the length, in number of
bytes, of the I-field to be transmitted. TBL = 0 is valid (no I-field). The CPU should access TBL
only when the SIU is not transmitting a frame, TBF = 0. The transmit buffer will not wrap around
after address 191 (BFH). A buffer end is automatically generated when address 191 is reached.
TBL is byte addressable.
Table 37. Transmit Buffer Length Register
7
6
5
4
3
2
1
0
TBL.7 TBL.6 TBL.5 TBL.4 TBL.3 TBL.2 TBL.1 TBL.0
4.10.8 Transmit Control Byte Register (TCB)
Table 38 presents the Transmit Control Byte Register, which contains the byte to be placed in the
control field of the transmitted frame during non-AUTO-mode transmission. The CPU should
access TCB only when the SIU is not transmitting a frame, TBF = 0. TCB is byte addressable.
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