IA186XL/IA188XL
16-Bit Microcontrollers
Data Sheet
July 6, 2011
Table 7. IA186XL Pin/Signal Descriptions (Continued)
Pin
Signal
test_n
Name
test_n/busy
PLCC
47
PQFP
29
LQFP
46
Description
test. Input. Active Low. When the test_n
input is high (i.e., not asserted), it causes the
IA186XL to suspend operation during the
execution of the WAIT instruction. Operation
resumes when the pin is sampled low
(asserted).
tmr in 0
tmr in 1
tmr in 0
tmr in 1
tmr out 0
20
21
22
59
58
57
77
76
75
timer 0 input. Input. Depending on the Timer
Mode programmed for Timer 0, this input is
used either as clock input or a control signal.
timer 1 input. Input. Depending on the Timer
Mode programmed for Timer 1, this input is
used either as clock input or a control signal.
timer 0 output. Output. Depending on the
Timer Mode programmed for Timer 0, this
output can provide a single pulse or a
repetitive waveform.
tmr out 0
tmr out 1
ucs_n
tmr out 1
ucs_n
23
34
56
45
74
62
timer 1 output. Output. Depending on the
Timer Mode programmed for Timer 1, this
output can provide a single clock or a
repetitive waveform.
upper chip select. Output. Active Low. This
pin provides a chip select signal that will be
asserted (low) whenever the address of a
memory bus cycle is within the address space
programmed for that output.
vcc
vcc
vss
9, 43
33, 34,
72, 73
10, 11, Power (VCC). This pin provides power for the
20, 50, IA186XL device. It must be connected to a
51, 61 +5V DC power source.
30, 31, Ground (VSS). This pin provides the digital
41, 70, ground (0V) for the IA186XL. It must be
vss
26,
60
12, 13,
53
80
connected to a VSS board plane.
wr_n
wr_n/qs1
63
8
27
write. Output. Active Low. When asserted
(low), wr_n indicates that data available on
the data bus are to be latched into the
accessed memory or I/O device.
x1
x2
x1
x2
59
58
16
17
32
33
x1 and x2 are inputs for the crystal
®
IA211080711-09
UNCONTROLLED WHEN PRINTED OR COPIED
http://www.Innovasic.com
Customer Support:
Page 30 of 75
1-888-824-4184
INNOVASIC [ INNOVASIC, INC ]
