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IA88C00 参数 Datasheet PDF下载

IA88C00图片预览
型号: IA88C00
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontroller]
分类和应用: 微控制器
文件页数/大小: 80 页 / 674 K
品牌: INNOVASIC [ INNOVASIC, INC ]
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IA88C00  
Data Sheet  
Microcontroller  
As of Production Version -01  
Figure 45. Port 2/3 A Interrupt Pending Register (P2AIP), R252 Bank 0  
Bit  
7
D7  
6
D6  
5
D5  
4
D4  
3
D3  
2
D2  
1
D1  
0
D0  
Initial Value  
Read/Write  
0
?
0
?
0
?
0
?
0
?
0
?
0
?
0
?
Read Only (writeable for reset puposes)  
The Port 2/3 A Interrupt Pending and Port 2/3 B Interrupt Pending registers represent the software  
interface to the negative edge-triggered flip-flops associated with external interrupt inputs. Each bit of  
these registers corresponds to an interrupt generated by an external source. When one of these registers is  
read, the value of each bit represents the state of the corresponding interrupt. When one of these registers  
is written to, a 1 in a bit position causes the corresponding edge-triggered flip-flop to be reset to 0. A 0  
causes no action.  
The software interfaces with these registers to poll the interrupts and also to reset pending interrupts as  
they are processed. Figure 45 shows the pin relationship.  
Figure 46. Port 2/3 B Interrupt Pending Register (P2BIP), R253 Bank 0  
Bit  
7
D7  
6
D6  
5
D5  
4
D4  
3
D3  
2
D2  
1
D1  
0
D0  
Initial Value  
Read/Write  
0
?
0
?
0
?
0
?
0
?
0
?
0
?
0
?
Read Only (writeable for reset puposes)  
The Port 2/3 A Interrupt Pending and Port 2/3 B Interrupt Pending registers represent the software  
interface to the negative edge-triggered flip-flops associated with external interrupt inputs. Each bit of  
these registers corresponds to an interrupt generated by an external source. When one of these registers is  
read, the value of each bit represents the state of the corresponding interrupt. When one of these registers  
is written to, a 1 in a bit position causes the corresponding edge-triggered flip-flop to be reset to 0. A 0  
causes no action.  
The software interfaces with these registers to poll the interrupts and also to reset pending interrupts as  
they are processed. Figure 46 shows the pin relationship.  
Copyright 2005  
Innovasic.com  
Innovasic Semiconductor  
ENG 21 0 050519-00  
www.Innovasic  
1.888.824.4184  
Page 42 of 80  
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