IA88C00
Data Sheet
Microcontroller
As of Production Version -01
Figure 47. External Memory Timing Register, R254 Bank 0
Bit
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
Initial Value
Read/Write
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
This register controls all the extended bus timing features.
D0 - DMA Select - If 0, DMA uses register file space. If 1, it uses Data Memory.
D1 - Stack Select - If 0, stack is located in register file space. If 1, it is located in Data Memory.
Figure 48. Interrupt Priority Register (IPR), R255 Bank 0
Bit
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
Initial Value
Read/Write
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
The Interrupt Priority register defines the priority order of the interrupt levels. Interrupts should be
globally disabled before writing to this register.
D0 - Group A - 0=IRQ0 > IRQ1; 1=IRQ1 > IRQ0.
D2 - Group B - 0=IRQ2>(IRQ3,IRQ4); 1=(IRQ3,IRQ4) > IRQ2.
D3 - Subgroup B - 0=IRQ3>IRQ4; 1=IRQ4>IRQ3.
D5 - Group C - 0=IRQ5>(IRQ6,IRQ7); 1=(IRQ6,IRQ7)>IRQ5.
D6 - Subgroup C - 0=IRQ6>IRQ7; 1=IRQ7>IRQ6.
Copyright 2005
Innovasic.com
Innovasic Semiconductor
ENG 21 0 050519-00
www.Innovasic
1.888.824.4184
Page 44 of 80
INNOVASIC [ INNOVASIC, INC ]
