IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Data Sheet
Bit and Byte Processors
BIP
The BIP consists of the DPLL, NRZI encoder/decoder, serial/parallel shifter, zero
insertion/deletion, shutoff logic and FCS generation/checking. The NRZI logic compares the
current bit to the previous bit to determine if the bit should be inverted. The serial shifter converts
the outgoing byte data to bit data and incoming bit data to byte data. The zero insert/delete
circuitry inserts and deletes zeros and also detects flags(01111110), go-aheads (GA) (01111111) and
aborts (1111111). The pattern 1111110 is detected as an early go-ahead that can be turned into a
flag in loop configurations. The shutoff detector is a three bit counter that is used to detect a
sequence of eight zeros, which is the shutoff command in loop mode transmissions. It is cleared
whenever a one is detected. The FCS logic performs the generation and checking of the FCS value
according to the polynomial described above. The FCS register is set to all 1’s prior to each
calculation. If a CRC error is generated on a receive frame the SIU will not interrupt the CPU and
the error will be cleared upon receiving an opening flag.
BYP
The BYP contains registers and controllers used to perform the manipulations required for SDLC
communications. The BYP registers may be accessed by the CPU (see SFR section above). The
BYP contains the SIU state machine that controls transmission and reception of frames.
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