IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Data Sheet
A.C. Characteristics
TA = -40°C to +85°C, VDD = 5V ± 10%, VSS = 0V, Load Capacitance = 87pF
External Program Memory Characteristics
Variable Clock 1/TCLCL
= 3.5 MHz TO 12 MHz
12 MHz Osc
Min Max
Symbol
Parameter
Unit
Min
Max
TLHLL
ALE Pulse Width
171
75
74
2TCLCL+4
TCLCL-8
TCLCL-9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TAVLL
TLLAX
TLLIV
TLLPL
TPLPH
TPLIV
TPXIX
TPXIZ
TPXAV
TAVIV
TAZPL
TCY
Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instr. In.
ALE Low to PSENn Low
PSENn Pulse Width
PSENn Low to Valid Instr. In
Input Instr. Hold After PSENn
Input Instr. Float After PSENn
PSENn to Address Valid
Address to Valid Instr. In
Address Float to PSENn
Machine cycle
298
4TCLCL-35
83
254
TCLCL
3TCLCL+4
215
76
3TCLCL-35
TCLCL-7
0
0
91
TCLCL+8
-9
373
5TCLCL-43
-9
996
12TCLCL
External Data Memory Characteristics
Variable Clock 1/TCLCL =
3.5 MHz TO 12 MHz
12 MHz Osc
Symbol
TRLRH
Parameter
RDn Pulse Width
Unit
Min
487
Max
Min
Max
6TCLCL-13
6TCLCL-13
TCLCL-9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TWLWH
TLLAX
TRLDV
TRHDX
TRHDZ
TLLDV
TAVDV
TLLWL
TAVWL
TQVWX
TQVWH
TWHQX
TRLAZ
TWHLH
WRn Pulse Width
487
74
Address Hold After ALE
RDn Low to Valid Data In.
Data Hold After RDn
383
5TCLCL-35
0
0
Data Float After RDn
165
633
708
2TCLCL-2
8TCLCL-34
9TCLCL-42
3TCLCL
ALE Low to Valid Data In
Address to Valid Data In.
ALE Low to RDn or WRn Low
Address to RDn or WRn Low
Data Valid to WRn Transistion
Data Setup Before WRn High
Data Held After WRn
250
325
76
563
86
250 3TCLCL
4TCLCL-8
TCLCL-7
7TCLCL-20
TCLCL+3
9
RDn Low to Address Float
RDn or WRn High to ALE High
9
83
83 TCLCL
TCLCL
Copyright 2003
innovASIC
ENG210010112-00
www.innovasic.com
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