IA82527
Data Sheet
CAN Serial Communications Controller
December 20, 2012
Errata No. 4
Problem: Majority Logic sample mode delays start of ACK bit transmission by one time
quanta.
Description: When the SPL bit (Bit 7) of the Bit Timing Register 1 (0x4F) is set to 1 to enable
the 3 sample Majority Logic mode, the transmission of the ACK bit in response to a received
CAN frame will be time shifted by 1 time quanta. With sufficient cable propagation delays and
propagation delays through CAN transceiver parts, CAN nodes on the CAN bus may see the
ACK bit being a 0 shifted over into its ACK delimiter bit time and flag this as an error.
Workaround: Use Single Sample mode instead of Majority Logic Sample Mode. The SPL bit
of the Bit Timing Register 1 (bit 7 of address 0x4F) should be a 0.
Errata No. 5
Problem: dsack0_n signal may not respond properly under certain conditions.
Description: Under certain conditions when the cs_n is asserted near the edge of xtal1 the
dsack0_n signal may not be properly generated. Depending on the clock divider settings sys_clk
and mem_clk at address 0x02, if the setup or hold time for cs_n with respect to xtal1 edge (rising
or falling) is violated, it is possible that dsack0_n will not respond to the cycle. This can cause
problems for systems that are dependent upon dsack0_n to occur before releasing cs_n to finish
the cycle. Note: The cycle still operates correctly in respect to reading or writing of data, only
the dsack0_n signal may not be generated.
Workaround:
Workaround #1: Do not use dsack0_n as part of the bus cycle timing.
Workaround #2: cs_n must meet the following timing relationship with regards to the xtal1 clock
edge:
sys clock divide edge of xtal1
setup (ns) hold (ns)
1 dsc=0
2 dsc=1
rise
fall
7
7
16
16
IA211080504-07
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