IA82527
Data Sheet
CAN Serial Communications Controller
December 20, 2012
7.
Errata
7.1
Summary
Version 2 Part Numbers
IA82527PQF44AR2
IA82527PLC44AR2
Errata
No.
Problem
1
The CPU writes to Msg Box 15 RAM cannot be read back if
MsgVal is set.
Exists
2
Setting the IntPnd bit to 1 from CPU interface will not cause
Interrupt.
Exists
3
4
5
An unintended Remote Frame may be generated.
Exists
Exists
Exists
Majority Logic sample mode delays start of ACK bit transmission
by one time quanta.
dsack0_n signal may not respond properly under certain
conditions.
7.2
Detail
Errata No. 1
Problem: The CPU writes to Msg Box 15 RAM cannot be read back if MsgVal is set.
Description: If the MsgVal bit (Bits [7–6]) of Msg Box 15 Control_0 register (0xF0) is set, any
CPU writes to the Msg Box 15 arbitration 0–3 registers (0xF2–0xF5), and data 0–7 registers
(0xF7–0xFE) will operate properly, however CPU reads of these registers will return unknown
data. In other words, any CPU data written to Msg Box 15 will not be read back correctly if the
MsgVal bit is set. If the MsgVal bit (Bits [7–6]) of Msg Box 15 Control_0 register (0xF0) is
reset, CPU data written can be read back normally.
Workaround: The workaround is to clear the MsgVal bit (Bits [7–6]) of Msg Box 15 Control_0
register (0xF0) before trying to read back any CPU data written to the Msg Box 15 arbitration
0–3 registers (0xF2–0xF5), and data 0–7 registers (0xF7–0xFE).
IA211080504-07
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